參數(shù)資料
型號(hào)： MT58V1MV18DT-10
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 1M X 18 CACHE SRAM, 5 ns, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 16/34頁(yè)
文件大?。?/td> 521K
代理商： MT58V1MV18DT-10
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03
23
2003 Micron Technology, Inc.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The SRAM incorporates a serial boundary scan test
access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are
excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
These balls can be left floating (unconnected), if the
JTAG function is not to be implemented. Upon power-
up, the device will come up in a reset state which will
not interfere with the operation of the device.
Figure 15:
TAP Controller State Diagram
NOTE:
The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 15. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most signifi-
cant bit (MSB) of any register. (See Figure 16.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-
out from the registers. The output is active depending
upon the current state of the TAP state machine. (See
Figure 15.) The output changes on the falling edge of
TCK. TDO is connected to the least significant bit
(LSB) of any register. (See Figure 16.)
Figure 16:
TAP Controller Block Diagram
NOTE:
X = 74 for all configurations.
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Bypass Register
0
Instruction Register
0
1
2
Identification Register
0
1
2
29
30
31
.
Boundary Scan Register*
0
1
2
.
x
.
Selection
Circuitry
Selection
Circuitry
TCK
TMS
TAP CONTROLLER
TDI
TDO
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