參數(shù)資料
型號(hào)： MT58V1MV18DT-10
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 1M X 18 CACHE SRAM, 5 ns, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 9/34頁(yè)
文件大?。?/td> 521K
代理商： MT58V1MV18DT-10
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03
17
2003 Micron Technology, Inc.
Notes
1. All voltages referenced to VSS (GND).
2. For 3.3V VDD:
Overshoot: VIH
+4.6V for t tKC/2 for I 20mA
Undershoot: VIL
-0.7V for t tKC/2 for I 20mA
Power-up:
VIH
+3.6V and VDD 3.135V for t
200ms
3. For 2.5V VDD:
Overshoot: VIH
+3.6V for t tKC/2 for I 20mA
Undershoot:VIL
-0.5V for t tKC/2 for I 20mA
Power-up: VIH
+2.65V and VDD 2.375V for t
200ms
4. The MODE and ZZ pins/balls have an internal
pull-up/pull-down and input leakage = ±10A.
5. VDDQ should never exceed VDD. VDD and VDDQ
can be connected together.
6. This parameter is sampled.
7. IDD is specified with no output current and
increases with faster cycle times. IDDQ increases
with faster cycle times and greater output loading.
8. “Device deselected” means device is in power-
down mode as defined in the truth table. “Device
selected” means device is active (not in power-
down mode).
9. Typical values are measured at 3.3V, 25C, and
10ns cycle time.
10. Typical values are measured at 2.5V, 25C, and
10ns cycle time.
11. Test conditions as specified with the output load-
ing shown in Figures 11 and 12 for 3.3V I/O and
Figures 13 and 14 for 2.5V I/O unless otherwise
noted.
12. Measured as HIGH above VIH and LOW below VIL.
13. This parameter is measured with the output load-
ing shown in Figure 12 for 3.3V I/O and Figure 14
for 2.5V I/O.
14. Refer to Technical Note TN-58-09, “Synchronous
SRAM Bus Contention Design Considerations,”
for a more thorough discussion of these parame-
ters.
15. OE# is a “Don’t Care” when a byte write enable is
sampled LOW.
16. A WRITE cycle is defined by at least one byte write
(BWa#–BWd#) being LOW, the byte write enable
(BWE#) active, and ADSC# LOW for the required
setup and hold times. A READ cycle is defined by
the byte write enable (BWE#) being HIGH or
ADSP# LOW for the required setup and hold
times.
17. This is a synchronous device. All addresses must
meet the specified setup and hold times when
either ADSC# or ADSP# is LOW and chip is
enabled. All other synchronous inputs must meet
the setup and hold times with stable logic levels
for all rising edges of CLK when the chip is
enabled. To remain enabled, chip enable must be
valid at each rising edge when either ADSC# or
ADSP# is LOW.
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