參數(shù)資料
型號: MT8920B
廠商: Mitel Networks Corporation
英文描述: ST-BUS Parallel Access Circuit(串行通信總線(ST-Bus)并行存取電路(在ST總線和并行系統(tǒng)間提供一個簡單接口))
中文描述: 意法半導(dǎo)體總線并行訪問電路(串行通信總線(圣總線)并行存取電路(在圣總線和并行系統(tǒng)間提供一個簡單接口))
文件頁數(shù): 7/29頁
文件大小: 215K
代理商: MT8920B
CMOS
MT8920B
3-9
Table 2. Mode 1 Address Map
NOTES:
X is don’t care
A
6
is bit D
4
of Control Register 1
Table 3. Control Register 1 Bit Definitions
ADDRESS BITS
REGISTERS
A
6
A
5
A
4
A
3
A
2
A
1
A
0
READ
WRITE
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
Rx0 - Channel 0
Rx0 - Channel 31
Control Register 1
Control Register 2
Interrupt Vector Register
Interrupt Flag Register 1
Interrupt Flag Register 2
Image Register 1
Image Register 2
Interrupt Mask Register 1
Interrupt Mask Register 2
Match Byte Register 1
Match Byte Register 2
Interrupt Channel Address 1
Interrupt Channel Address 2
Rx0 - Channel 0
Rx0 - Channel 31
Tx0 - Channel 0
Tx0 - Channel 31
Control Register 1
Control Register 2
Interrupt Vector Register
-
-
-
-
Interrupt Mask Register 1
Interrupt Mask Register 2
Match Byte Register 1
Match Byte Register 2
Interrupt Channel Address 1
Interrupt Channel Address 2
Tx1 - Channel 0
Tx1 - Channel 31
Bit
Name
Description
7
(Unused)
6
IRQRST
Interrupt Reset.
This bit, when set high, automatically clears the Interrupt Flag Register
and the Interrupt Image Register without these registers being serviced. This bit
automatically resets to zero after the register clear is completed.
5
RAMCON
RAM Configuration.
This bit configures Tx0, Tx1 and Rx0 RAMS for 32 or 24 byte
operation. D
5
= 0 for 32 channel; D
5
= 1 for 24 channel.
Address Bit A6.
This bit extends the addressing range for access to Tx1 memory.
4
A
6
3
IRQ2MODE
Interrupt Source 2 Mode Select.
This bit configures the source 2 interrupt generator.
D
3
= 0 selects “static” interrupt mode; D
3
= 1 selects “dynamic” interrupt mode.
Interrupt Source 1 Mode Select.
This bit configures the source 1 interrupt generator.
D
2
= 0 selects “static” interrupt mode; D
2
= 1 selects “dynamic” interrupt mode.
Interrupt Source 2 Enable.
IRQ2EN = 1 enables interrupts to occur from source 2.
2
IRQ1MODE
1
IRQ2EN
0
IRQ1EN
Interrupt Source 1 Enable.
IRQ1EN = 1 enables interrupts to occur from source 1.
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