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參數(shù)資料
| 型號： | MT90210 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Rate Parallel Access Circuit(并行多路存取電路) |
| 中文描述： | 多速率并行訪問電路（并行多路存取電路） |
| 文件頁數(shù)： | 7/27頁 |
| 文件大?。?/td> | 133K |
| 代理商： | MT90210 |
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Preliminary Information
MT90210
2-151
Figure 5- External Double Buffer Operation and
Memory Arrangement in Modes 4 and 5.
Bidirectional Operation:
Serial output channel
timeslots can be tri-stated by setting the OEser input
pin high during a specific parallel channel timeslot.
Note that when operating in bidirectional mode, the
MT90210’s I/O buffers on the serial port are
permanently at high impedance and the control of
contention on the serial bus has to be done by the
user through the OEser input pin. In modes 1, 2, 4
and 5 all of the transmit channels on the serial port
side are copied back to the memory interface. This is
true only in bidirectional modes (i.e., modes 1, 2, 4
and 5). Note that only the transmit (output) channels
are copied back to the memory and that the input
channels remain unaffected.
For a specific time-slot sampled at the external
memory parallel interface, the respective OEser
input pin must be in the desired state; i.e., the
sampling of the OEser input is synchronized with the
parallel byte read at the P0-P7 lines.
Functional operation of the MT90210
device at the parallel interface for
modes 1, 2, and 3
Figures 8, 12, and 13 depict the parallel port READ
and WRITE operation of the MT90210 device. The
state of the signals R/W1, R/W2 and Strobe defines
a valid Read or a valid Write operation. During a
valid READ operation the signals Strobe and R/W2
stay LOW while the signal R/W1 is always HIGH. For
the valid WRITE operation the signal R/W2 always
stays HIGH while the signals R/W1 and Strobe
toggle. Table 3 represents the sequence of events as
depicted in Figure 12 during the last channel at the
end of an ST-BUS frame. The MT90210 device
repeats the same sequence of operation during the
entire frame. For example, during channel 127 at the
end of an ST-BUS frame the MT90210 will write
channel 126 (streams 0 to 11) and read from channel
1 (streams 12 to 23) of the next frame as shown in
Table 3. Note that there is a two channel difference
between a write and a read sequence. In mode 1
and mode 2, the MT90210 device performs a group
of writes and a group of reads separated by 8 PCLK
periods, while for modes 3, 4 and 5 they are
separated by 4 PCLK periods.
Functional operation of the MT90210
device at the parallel interface for mode
4 and mode 5
Table 4 represents the sequence of events when the
MT90210 device is operating at a mixed rate of
operation (mode 4 and mode 5) as depicted in Figure
13. The MT90210 device repeats the same sequence
of operation as shown in Table 4 throughout the entire
frame. In mode 4 and mode 5 the MT90210 device is
configured with 24 bidirectional serial streams and split
into two different rates: S0 to S15 operate at 2.048
Mb/s data rates (512 time-slots) and streams S16 to
S23 run at 8 Mb/s data rates (1024 time-slots). In this
mode, 12 writes are carried out during a parallel port
write cycle and 12 reads during a read cycle. Of each
group of 12, 8 are dedicated to the high-speed 8.192
Mb/s links, therefore four slots are available for the
2.048 Mb/s links. To process all the 16 streams
devoted for 2.048 Mb/s, four separate write or read
cycles are required (these slots are denoted with the
suffix "a", "b", "c", "d" in Figure 13). Each write or
read cycle will use four time-slots. For example, read
or write cycle "a" uses streams S0 to S3, read or
write cycle "b" uses streams S4 to S7, read or write
cycle "c" uses streams S8 to S11 and read or write
cycle "d" uses streams S12 to S15 (see Table 4).
There is a two channel difference between a read
and write sequence for 2 Mb/s data and an eight
channel difference for 8 Mb/s data.
BLOCK 0
0000
0400
0C00
0800
BLOCK 1
1000
1C00
1800
1FFF
512 bytes for
S0-S15 TX
1024 bytes for
S16-S23 TX
1400
01FF
09FF
11FF
19FF
1024 bytes for
S16-S23 RX
512 bytes for
S0-S15 RX
512 bytes for
S0-S15 TX
1024 bytes for
S16-S23 TX
1024 bytes for
S16-S23 RX
512 bytes for
S0-S15 RX
S0-S15 bidirectional 2.048Mb/s streams
S16-S23 bidirectional 8.192Mb/s streams
Address outputs used: A0-A12
unused memory space
Legend:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90210 | Multi-Rate Parallel Access Circuit |
| MT90210AL | Multi-Rate Parallel Access Circuit |
| MT90220 | Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備（八端口ATM IMA和UNI處理器）) |
| MT90221 | Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）) |
| MT90401 | SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90210AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Rate Parallel Access Circuit |
| MT90220 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Octal IMA/UNI PHY Device |
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
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