參數(shù)資料
型號： MT9074AP
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁數(shù)： 36/122頁
文件大小： 372K
代理商： MT9074AP
MT9074
Advance Information
36
Bipolar Violation Error Counter (BPV15-BPV0)
The bipolar violation error counter will count bipolar
violations or encoding errors that are not part of
B8ZS encoding. This counter BPV15-BPV0 is 16 bits
long (page 4H, addresses 16H and 17H) and is
incremented once for every BPV error received. It
should be noted that when presetting or clearing the
BPV error counter, the least significant BPV counter
address should be written to before the most
significant location.
There are two maskable interrupts associated with
the bipolar violation error measurement. A single
error may generate an interrupt (enable by setting
BPVI high - bit 3 of the Interrupt Mask Word One,
page 1H, address 1CH). A counter overflow interrupt
may be enabled by setting control bit BPVO high - bit
3 of Interrupt Mask Word Two (page 1H, address
1DH).
PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS
comparison; one for errors and one for time. Any
errors that are detected in the receive PRBS will
increment the PRBS Error Rate Counter of page
04H, address 10H. Writes to this counter will clear an
8 bit counter, PSM7-0 (page 01H, address 11H)
which counts receive CRC multiframes. A maskable
PRBS counter overflow (PRBSO) interrupt (page 1,
address 1DH) is associated with this counter.
CRC Multiframe Counter for PRBS (PSM7-0)
This eight bit counter counts receive CRC-4
multiframes. It can be directly loaded via the
microport. The counter will also be automatically
cleared in the event that the PRBS error counter is
written to by the microport. This counter is located on
page 04H, address 11H.
E1 Counters
Errored FAS Counter (EFAS7-EFAS0)
An eight bit Frame Alignment Signal Error counter
EFAS7 - EFAS0 is located on page 04H address
13H, and is incremented once for every receive
frame alignment signal that contains one or more
errors.
There are two maskable interrupts associated with
the frame alignment signal error measurement. FERI
(page 01H, address 1CH) is initiated when the least
significant bit of the errored frame alignment signal
counter toggles, and FERRO (page 01H, address
1DH) is initiated when the counter changes from
FFH to 00H.
E-bit Counter (EC9-0)
E-bit errors are counted by the MT9074 in order to
support compliance with ITU-T requirements. This
ten bit counter is located on page 04H, addresses
14H and 15H respectively. It is incremented by single
error events, with a maximum rate of twice per CRC-
4 multiframe.
There are two maskable interrupts associated with
the E-bit error measurement. EBI (page 1, address
1CH) is initiated when the least significant bit of the
counter toggles, and FEBEO (page 01H, address
1DH) is initiated when the counter overflows.
Bipolar Violation Error Counter (BPV15-BPV0)
The bipolar violation error counter will count bipolar
violations or encoding errors that are not part of
HDB3 encoding in E1 mode. This counter BPV15-
BPV0 is 16 bits long (page 4H, addresses 16H and
17H) and is incremented once for every BPV error
received. It should be noted that when presetting or
clearing the BPV error counter, the least significant
BPV counter address should be written to before the
most significant location.
In E1 mode, there are two maskable interrupts
associated
with
the
measurement. BPVI (page 01H, address 1CH) is
initiated when the l significant bit of the BPV error
counter toggles. BPVO (page 01H, address 1DH) is
initiated when the counter changes from FFFFH to
0000H.
bipolar
violation
error
CRC-4 Error Counter (CC9-0)
CRC-4 errors are counted by the MT9074 in order to
support compliance with ITU-T requirements. This
ten bit counter is located on page 04H, addresses
18H and 19H in E1 mode. It is incremented by single
error events, which is a maximum rate of twice per
CRC-4 multiframe.
There is a maskable interrupt associated with the
CRC error measurement. CRCIM (page 01H,
address 1CH) is initiated when the least significant
bit of the counter toggles, and CRCOM (page 01H,
address 1DH) is initiated when the counter
overflows.
PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS
comparison; one for errors and one for time. Any
errors that are detected in the receive PRBS will
increment the PRBS Error Rate Counter of page
04H, address 10H. Writes to this counter will clear an
8 bit counter, PSM7-0 (page 01H, address 11H)
which counts receive CRC multiframes. A maskable
相關PDF資料
PDF描述
MT9074 T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
MT9074AP1 制造商:Microsemi Corporation 功能描述:T1/E1/J1 SGLE CHIP XSCR 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX SGL T1/E1 68PLCC 制造商:Microsemi Corporation 功能描述:IC TXRX SGL T1/E1 68PLCC
MT9074APR 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
MT9074APR1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel
MT9075 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver
MT9075A 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:E1 Single Chip Transceiver
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