參數(shù)資料
型號: MT9080B
廠商: Mitel Networks Corporation
英文描述: SMX - Switch Matrix Module(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開關(guān)矩陣模塊)
中文描述: SMX -開關(guān)矩陣模塊(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開關(guān)矩陣模塊)
文件頁數(shù): 12/25頁
文件大?。?/td> 123K
代理商: MT9080B
MT9080B
CMOS
2-112
Figure 16 - 1024 Channel Switch Timing
CK
FP #2
Internal
Counter
(Read
Address)
Data Output
D0o-D15o
DATA MEMORY TIMING
Data Output
D0o-D15o
FP #1
Internal Counter
(Write Address)
Data In
D0i-D15i
CONNECTION MEMORY TIMING
y
1023
0
1
2
3
4
5
1022
1023
0
1
2
3
4
1021
1022
1023
0
1
2
3
1021
1022
1023
0
1
2
1021
1022
1023
0
1
2
addresses
SMX #1 Data Input/Output Frame Boundary
Note 1: Address is latched into the Data Memory by the first positive clock edge in a timeslot (edge
for Ch. 0). Data will be
clocked out by the first positive clock edge in the next timeslot (edge
y
for Ch. 0).
Note 2: Data is latched into the Data Memory by the first rising edge in a timeslot (edge
for Ch. 0) and is written into the
memory location addressed by the internal counter with the next rising edge (edge
for Ch. 0).
addresses
ahead of time; i.e., one channel before the
addressed data is clocked out of the Data Memory. It
may be necessary to provide an external bus enable
one channel ahead of time in applications where
precharging of the external data bus is required. In
other applications where no precharge is required,
control bit from the next channel may be used in
order to ensure that the external bus is enabled at
the same time as the channel is being clocked out of
the device.
The Change Detect (CD) output of the Connection
Memory is used to interrupt the MPU. As mentioned
in the Pin and Functional descriptions, CD goes low
when the internal CRC performed by the device
indicates a change in memory contents. This feature
is particularly useful in switching applications where
the Connection Memory is configured once and is
not modified for long periods of time, e.g., in network
digital
access
crossconnect
inadvertent corruption of the memory contents will
cause CD to interrupt the processor.
systems.
Any
Figure 17 - Mapping of Address and Control Signals onto Connect Memory Data Bits
D15 - D14
Unused
D13
External
Driver
Enable
D12
DM-1 or
DM-2
Select
D11
Message
Enable
D10
ODE
Control
D9 - D0
Source
Channel
Address
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