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參數(shù)資料
| 型號(hào)： | MT9080B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | SMX - Switch Matrix Module(用于消費(fèi)類(lèi)轉(zhuǎn)換應(yīng)用的開(kāi)關(guān)矩陣模塊) |
| 中文描述： | SMX -開(kāi)關(guān)矩陣模塊（用于消費(fèi)類(lèi)轉(zhuǎn)換應(yīng)用的開(kāi)關(guān)矩陣模塊） |
| 文件頁(yè)數(shù)： | 7/25頁(yè) |
| 文件大?。?/td> | 123K |
| 代理商： | MT9080B |
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CMOS
MT9080B
2-107
This mode provides minimum delay through the SMX
for any switching configuration.
Data Memory Mode-2
Data Memory Mode-2 is designed for use in
constructing a 1024 by 1024 channel double buffered
switch. This mode is similar in most respects to Data
Memory Mode-1. The double buffering is achieved by
dividing the internal 2048 memory into two equal
blocks. In a single frame, data is written into the first
block and read from the second. In the next frame,
the data will be written into the second and read from
the first (see Figure 6). Frame sequence integrity of
the data will be maintained for all switching
configurations if the output frame is delayed by one
channel with respect to the input frame. In this case,
data clocked into the device during any of the
channels in the current frame will be clocked out in
the next frame. However, if the input and output
frames are aligned, then data switched from any
input channel to output channels 0 or 1 will be
clocked out one frame after the next - consequently
frame sequence integrity is not maintained for
channels 0 or 1. Frame sequence integrity will be
maintained for data switched to any of the other
output channels. (See SMX/PAC Application Note,
MSAN-135, for more information.)
It is possible to switch between Data Memory
Mode-1 and Mode-2 on a per timeslot basis.
Data Memory Mode-3
This mode is similar to Data Memory Mode-1.
However, there is no restriction on the minimum
acceptable clock frequency or frame rate. In this
mode, the size of the switching matrix depends on
the clock and frame rates provided as per the
following relationship:
where
S
is the number of channels in the switching
matrix
F
FP
is the frame pulse frequency in Hz, and
F
CK
is the clock frequency in Hz. The following table
shows how the size of a switching matrix can be
varied by selecting a suitable combination of clock
and frame rates.
It is not possible to switch between Data Memory
Mode-3 and other modes on per-timeslot basis.
Connect Memory Mode -1
In Connect Memory Mode-1, the input data bus is
bidirectional. Internal memory locations can be
randomly accessed via the microprocessor bus. The
pinout of the device in this mode is illustrated in
Figure 7.
CK (MHz)
FP (kHz)
Number of channels in
the switching matrix
16.384
16.384
16.384
12.288
12.288
8.192
8.192
4
8
16
4
8
4
8
2,048
1,024
512
1,536
768
1,024
512
S=
F
CK
2 X F
FP
Figure 6 - Data Memory Mode-2 Functional Timing
CK
Data
Input
Data
Output
FRAME 0
FRAME 1
FRAME 2
FRAME 1
FRAME 2
1023
0
1
1023
0
1
0
1
0
1
Written to Block 0
Written to Block 1
Read from Block 1
Read from Block 0
FRAME 0
Written to
Block 1
Read from
Block 0
1023
1023
Note:
No input and output channel alignment is implied in the example shown above. It is assumed that the frame pulse for the
connection memory used to generate adresses for the read operation has a specific phase relationship with respect to the Data
Memory frame pulse.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9080BP | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:CMOS SMX - Switch Matrix Module |
| MT9081 | 制造商:MARKTECH 制造商全稱(chēng):Marktech Corporate 功能描述:3 Leaded Tri-State LED Lamps |
| MT90810 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:CMOS Flexible MVIP Interface Circuit |
| MT90810AK | 制造商:Microsemi Corporation 功能描述: |
| MT90812 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
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