參數(shù)資料
型號(hào)： MT9080B
廠商： Mitel Networks Corporation
英文描述： SMX - Switch Matrix Module(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開(kāi)關(guān)矩陣模塊)
中文描述： SMX -開(kāi)關(guān)矩陣模塊（用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開(kāi)關(guān)矩陣模塊）
文件頁(yè)數(shù)： 9/25頁(yè)
文件大?。?/td> 123K
代理商： MT9080B
CMOS
MT9080B
2-109
The device can perform either a read or a write,
depending on the level asserted at the R/W pin.
When R/W is high, the contents of the memory
addressed by the internal counter will be clocked out
on to the output data bus. Setting R/W low will
enable data on the input data bus to be written into
the device. During a write operation, the output bus
is actively driven by the data latched out in the
previous read operation.
Data is clocked in or out of the device on the positive
edge of the clock. See Figure 11.
Figure 11 - Counter Mode Functional Timing
External Mode
The external mode, which is designed for use in
2048 switching applications, permits random access
to the memory both for input and output operations.
The pinout for external mode is shown in Fig. 12.
The address asserted on the external address bus is
used to specify the memory location to be accessed
for the read or write operation. The level asserted on
R/W during a specific clock period determines
whether the addressed memory is written to or read
from. During a write operation, the output data bus is
actively driven with data latched out in the previous
read operation.
Data is clocked into or out of the device on the
positive edges of the clock as shown in Figure 13.
Shift Register Mode
In this mode, data clocked into the SMX is delayed
by a number of clock cycles before being clocked out
of the device. The delay introduced (in number of
clock cycles) is equal to two times the binary value of
the address latched into the device plus 2. For
example, if the address asserted is Hex 02, the delay
through the switch is equal to six clock cycles.
Figure 12 - External Mode Pinout
Figure 13 - External Mode Functional Timing
Maximum permissible delay is equal to 4096 clock
cycles.
The pertinent timing parameters are illustrated in
Figure 14. Data is clocked in and out of the device
with rising edge of the clock.
The address is latched in with the negative edge of
DS while the CS is low.
CK
FP
Internal
Counter
Data Clocked Out
(R/W High)
Data Clocked In
(R/W LOW)
2047
0
1
2
3
0
1
2
2047
0
1
2
3
16
D0
i
-D15
i
CK
FP
D0
o
-D15
o
CS
DS
CD
R/W
A0-A11
X
Y
Z
16
ODE
DTA
ME
1
0
1
All other inputs should
be tied Low
CK
FP
ADDR
Data In
(R/W Low)
Data Out
(R/W High)
CH X
CH Y
CH Z
X
Y
Z
CH X
CH Y
CH Z
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