參數(shù)資料
型號： MT90840AL
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Distributed Hyperchannel Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： 14 X 20 MM, 2.80 MM HEIGHT, MO-112CC-1, MQFP-100
文件頁數(shù)： 22/51頁
文件大?。?/td> 512K
代理商： MT90840AL
MT90840
Data Sheet
2-252
the DTA pin will be asserted (as the data is stored in
the write-pipeline) but the next CPU access will not
see DTA asserted. No clocks are necessary for
register accesses (but if the write-pipeline is hung,
the registers cannot be accessed). If the MT90840 is
hung due to a CPU read of a memory with a missing
clock, the hang can be cleared by ending the read
access. If the MT90840 is hung due to a CPU write
to a memory with a missing clock, the hang can be
cleared by applying a hardware RESET to the
MT90840.
Detecting Clock Presence
After it is set, the BPE bit is cleared within 2 frames
of the C4/8 clock (i.e. within 250
μ
sec). If this bit is
cleared by the MT90840, the CPU can deduce that
the C4/8 clock is present. In TM3, in TM4, and in
TM2 with INTCLK asserted, C4/8 is internally
generated from PCKR, and if the BPE bit is cleared
by the MT90840, the CPU can deduce that the
PCKR clock is present.
Clock Quality and TM1 TPCM Access Integrity
In Timing Mode 1 the parallel transmit frame pulse
PPFTo must be held in phase with the serial bus
frame pulse input (F0i). This is performed
automatically by the MT90840 with an internal
correction event, which moves the PPFTo output. In
normal TM1 operation the correction happens once
on initialization, and does not happen again as long
as the C4/8 and PCKT clocks stay phase-locked.
If the clocks lose their phase lock, the MT90840 will
assert an automatic correction, and set the TXPAA
interrupt bit high. The transmit parallel port data, the
CTO control data and the TX frame pulse (PPFTo)
will all jump phase due to this correction, causing
one errored TDM frame.
If a CPU write to the Transmit Path Connection
Memory is occurring during the one PCKT clock
cycle that clocks the correction, there is a chance
that the write data will go to address 0, rather than
the intended address. To avoid this it is necessary to
keep clocks stable during TPCM programming in
TM1 (including not using DIN while programming). If
there is some doubt about the quality of the clocks in
a particular application, options include:
-1- Program the TPCM in TM2, or TM2 with internal
clocks (INTCLK=1), where this clock correction does
not occur.
-2- Monitor the TXPAA interrupt bit during TPCM
programming, and check the intended address, and
address 0, if a TXPAA alarm occurs.
-4- Read/verify address 0 after a block of TPCM
writes. If address 0 is corrupted, one of the writes
occurred during a clock correction.
Clock Quality and TM2 RPCM Access Integrity
In Timing Mode 2 the serial frame pulse F0o must be
held in phase with the parallel port RX frame pulse
(PPFRi). This is performed automatically by the
MT90840 with an internal correction event, which
inverts the phase of the SPCKo output. In normal
operation
the
correction
initialization, and does not happen again as long as
the C4/8 and PCKR clocks stay phase-locked.
happens
once
on
If the clocks lose their phase lock, the MT90840 will
assert an automatic correction, and set the RXPAA
interrupt bit high. The serial port data and the ST bus
frame pulse (F0o) will jump phase due to this
correction, causing one errored TDM frame. The
PPCE bit indicates a change in framing at the
receive parallel port which may cause a “cascade”
correction at SPCKo.
If a CPU write to the Receive Path Connection
Memory is occurring during the one 4.096 MHz clock
cycle that clocks the correction, there is a chance
that the write data will go to Stream0-Channel0, or
Stream1-Channel0,
rather
address. To avoid this it is necessary to keep clocks
stable during RPCM programming in TM2 (including
not using DIN while programming). If there is some
doubt about the quality of the clocks in a particular
application, options include:
-1- Program RPCM in TM1, where this correction
does not occur.
-2- Program RPCM in TM2 with Internal Clock mode,
(INTCLK=1) where this correction does not occur.
-3- Monitor the RXPAA interrupt bit during RPCM
programming, and check the ST0-Ch0 and ST1-Ch0
addresses if an alarm occurs.
-4- Read/verify ST0-Ch0 and ST1-Ch0 after a block
of RPCM writes. If either is corrupted, one of the
writes occurred during a clock correction.
than
the
intended
Memory Block-Programming
The MT90840 allows the user to program one value
into the entire Transmit Path Connect Memory High,
or Receive Path Connect Memory High, with a single
register write. This feature allows the four most
significant bits of each byte in the TPCM High, or
RPCM High, to be automatically programmed with
the value of the 4 PBD bits of the GPM register. This
eases system initialization by allowing all channels to
be placed in high-impedance, or all channels to be
placed in bypass. The procedure works as follows:
a)
The SEL2-0 bits in the Control Register are used
to select Block-Programming for either the
TPCM High, or the RPCM High blocks. It is also
necessary to select the serial port mode (with
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MT90840AP1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 512 X 2430/512 X 512/2.373K X 2.373K 5V 84PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH DHS 84PLCC 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH DHS 84PLCC
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