參數(shù)資料
型號(hào): MT90840AL
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Distributed Hyperchannel Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝: 14 X 20 MM, 2.80 MM HEIGHT, MO-112CC-1, MQFP-100
文件頁數(shù): 34/51頁
文件大?。?/td> 512K
代理商: MT90840AL
MT90840
Data Sheet
2-264
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 17 - Output Test Load
10 STo Delay from High-Z to Active
2.048 and 4.096 Mbps (TM2 &TM3)
2.048 and 4.096 Mbps (TM1)
8.192 Mbps (STio0-3)
11 STo Output Delay from SPCKo
(TM2 & TM3, 2.048 and 4.096 Mbps)
t
za
38
50
26
40
64
ns
ns
ns
ns
ns
C
L
=30pF, R
L
=1K
STo Output Delay from 4.096 MHz C4/8
input (TM1)
STo 8.192 Mbps Output Delay from
C4/8 input (TM1, 2 & 3; STi/o0-3)
12 STi Input Setup Time from SPCKo
output edge (2.048 and 4.096 Mbps)
t
sod
52
72
28
43
ns
ns
ns
ns
ns
C
L
=30pF
C
L
=150pF
C
L
=30pF
C
L
=150pF
C
L
=30pF
C
L
=150pF
SPCKo C
L
=30pF
SPCKo C
L
=150pF
STi Input Setup Time from C4/8 input
edge in TM1 (2.048 and 4.096 Mbps)
STi Input Setup Time from C4/8 input
edge at 8.192 Mbps (STi/o0-3)
13 STi Input Hold Time from SPCKo output
edge (2.048 and 4.096 Mbps)
t
stis
28
41
0
0
9
2
ns
ns
ns
TM1 and TM2,
STi0-3, STo0-3
SPCKo C
L
=30pF
SPCKo C
L
=150pF
STi Input Hold Time from C4/8 input
edge in TM1 (2.048 and 4.096 Mbps)
STi Input Hold Time from C4/8 input
edge at 8.192 Mbps
t
stih
20
13
ns
ns
TM1 and TM2,
STi0-3, STo0-3
AC Electrical Characteristics
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
Output
Pin
Test Point
C
L
V
SS
S1
R
L
V
DD
S2
V
SS
S1 is open circuit except
when testing output levels
or high impedance states.
S2 is switched to VDD or
V
SS
when testing output
levels or high impedance
states
.
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