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參數(shù)資料
| 型號(hào)： | MT9160 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| 中文描述： | ISO2 - 5伏的CMOS多精選編解碼器（MFC）中 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 402K |
| 代理商： | MT9160 |
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MT9160
Preliminary Information
7-84
Codec, Digital gain and tone generation) and to
provide the channel timing requirements.
The MT9160 uses only the first four channels of the
32 channel frame. These channels are always
defined, beginning with Channel 0 after the frame
pulse, as shown in Figure 7 (ST-BUS channel
assignments).
The first two (D & C) Channels are enabled for use
by the DEN and CEN bits respectively, (Control
Register 2, address 04h). ISDN basic rate service
(2B+D) defines a 16 kb/s signalling (D) Channel. The
MT9160 supports transparent access to this
signalling channel. ST-BUS basic rate transmission
devices, which may not employ a microport, provide
access to their internal control/status registers
through the ST-BUS Control (C) Channel. The
MT9160
supports
microport
C-Channel.
access
to
this
DEN - D-Channel
In ST-BUS mode access to the D-Channel (transmit
and receive) data is provided through an 8-bit read/
write register (address 06h). D-Channel data is
accumulated in, or transmitted from this register at
the rate of 2 bits/frame for 16 kb/s operation (1 bit/
frame for 8 kb/s operation). Since the ST-BUS is
asynchronous, with respect to the microport, valid
access to this register is controlled through the use
of an interrupt (IRQ) output. D-Channel access is
enabled via the (DEn) bit.
DEn:
When 1, ST-BUS D-channel data (1 or 2 bits/frame
depending on the state of the D8 bit) is shifted into/
out of the D-channel (READ/WRITE) register.
When 0, the receive D-channel data (READ) is still
shifted into the proper register while the DSTo
D-channel timeslot and IRQ outputs are tri-stated
(default).
D8:
When 1, D-Channel data is shifted at the rate of 1 bit/
frame (8 kb/s).
When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
frame. By arbitrarily assigning ST-BUS frame n as
the
reference
frame,
microprocessor D-Channel read and write operations
are performed, then:
during
which
the
(a) A microport read of address 04 hex will result in a
byte of data being extracted which is composed of
four di-bits (designated by roman numerals I,II,III,IV).
These di-bits are composed of the two D-Channel
bits received during each of frames n, n-1, n-2 and
n-3. Referring to Fig. 8a: di-bit I is mapped from
frame n-3, di-bit II is mapped from frame n-2, di-bit III
is mapped from frame n-1 and di-bit IV is mapped
from frame n.
The D-Channel read register is not preset to any
particular value on power-up (PWRST) or software
reset (RST).
(b) A microport write to Address 04 hex will result in
a byte of data being loaded which is composed of
four di-bits (designated by roman numerals I, II, III,
IV). These di-bits are destined for the two D-Channel
bits transmitted during each of frames n+1, n+2, n+3,
n+4. Referring to Fig. 8a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is
mapped to frame n+3 and di bit IV is mapped to
frame n+4.
If no new data is written to address 04 hex , the
current
D-channel
register
continuously re-transmitted. The D-Channel write
register is preset to all ones on power-up (PWRST)
or software reset (RST).
contents
will
be
Figure 7 - ST-BUS Channel Assignment
F0i
DSTi,
DSTo
LSB first
for D-
Channel
MSB first for C, B1- & B2-
Channels
CHANNEL 0
D-channel
CHANNEL 1
C-channel
CHANNEL 2
B1-channel
CHANNEL 3
B2-channel
CHANNELS 4-31
Not Used
125
μ
s
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9160AE | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT9160AS | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT9160BN | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT91610 | Programmable Ringing SLIC(可編程振鈴用戶線路接口電路（帶一個(gè)外部驅(qū)動(dòng)器）) |
| MT9161B | ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT91600 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Programmable SLIC |
| MT91600AN | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Programmable SLIC |
| MT91600AN1 | 制造商:Microsemi Corporation 功能描述:SLIC 1CH 55DB 32MA 5V 28SSOP - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:SLIC 1CH 55DB 32MA 5V 28SSOP - Rail/Tube |
| MT91600ANR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Programmable SLIC |
| MT91600ANR1 | 制造商:Microsemi Corporation 功能描述:SLIC 1CH 55DB 32MA 5V 28SSOP - Tape and Reel |
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