參數(shù)資料
型號(hào)： MTA81010-XT/SO
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28
封裝： 0.300 INCH, SOIC-28
文件頁(yè)數(shù)： 11/76頁(yè)
文件大小： 745K
代理商： MTA81010-XT/SO
1995 Microchip Technology Inc.
DS39005D-page 19
MTA81010
3.2.7
W (WORKING) REGISTER
The W register holds the second operand in two
operand instructions and/or supports the internal data
transfer.
3.2.7.1
TIME OUT AND POWER DOWN STATUS
BITS (TO, PD )
The TO and PD bits in the STATUS register can be
tested to determine if a RESET condition has been
caused by a Watchdog Timer time-out, a power-up
condition, or a wake-up from SLEEP by the Watchdog
Timer or MCLR pin.
These STATUS bits are only affected by events listed in
Table 3-5.
TABLE 3-5:
EVENTS AFFECTING TO/PD
STATUS BITS
Event
TO
PD
Remarks
Power-up
11
WDT Timeout
0x
No effect on PD
SLEEP
instruction
10
CLRWDT
instruction
11
A WDT timeout will occur regardless of the status of
the TO bit.
A SLEEP instruction will be executed,
regardless of the status of the PD bit.
Table 3-6
reflects the status of
TO and PD after the
corresponding event.
TABLE 3-6:
TO/PD STATUS AFTER
RESET
TO
PD
RESET was caused by
00
WDT wake-up from SLEEP
01
WDT time-out (not during SLEEP)
10
MCLR wake-up from SLEEP
11
Power-up
uu
= Low pulse on MCLR input
The TO and PD bits maintain their status (u) until an
event of Table 4-3 occurs. A low-pulse on the MCLR
input does not change the TO and PD status bits.
相關(guān)PDF資料
PDF描述
MTA81010S-LPI/SO 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28
MTA81010-LPI/P 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28
MTA81010S-RCI/SO 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28
MTA81010-XTI/P 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28
MTA81010T-XT/SO 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28
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