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參數(shù)資料
| 型號： | MTA81010-XT/SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數(shù)： | 62/76頁 |
| 文件大?。?/td> | 745K |
| 代理商： | MTA81010-XT/SO |
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1995 Microchip Technology Inc.
DS39005D-page 65
MTA81010
19.9
Write Protection
The 24LC01B can be used as a serial ROM when the
WP pin is connected to SEEVDD. Programming will be
inhibited and the entire memory will be write-protected.
19.10
Read Operation
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
19.10.1 CURRENT ADDRESS READ
The 24LC01B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24LC01B
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate
a stop condition and the 24LC01B
discontinues transmission (Figure 19-5).
19.10.2 RANDOM READ
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC01B as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC01B will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate
a stop condition and the 24LC01B
discontinues transmission (Figure 19-6).
19.10.3 SEQUENTIAL READ
Sequential reads are initiated in the same way as a
random read except that after the 24LC01B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LC01B to transmit the next sequentially
addressed 8-bit word (Figure 19-7).
To provide sequential reads the 24LC01B contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
19.10.4 NOISE PROTECTION
The 24LC01B employs a VDD threshold detector circuit
which disables the internal erase/write logic if the VDD
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
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