參數(shù)資料
型號: MTA81010-XT/SO
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28
封裝: 0.300 INCH, SOIC-28
文件頁數(shù): 65/76頁
文件大?。?/td> 745K
代理商: MTA81010-XT/SO
MTA81010
DS39005D-page 68
1995 Microchip Technology Inc.
TABLE 20-2:
AC CHARACTERISTICS: 24LC01B
FIGURE 20-2: BUS TIMING DATA
STANDARD
MODE
VCC = 4.5-5.5V
FAST MODE
Parameter
Symbol
Min
Max
Min
Max
Units
Remarks
Clock frequency
FCLK
01000400
kHz
Clock high time
THIGH
4000
600
ns
Clock low time
TLOW
4700
1300
ns
SDA and SCL rise time
TR
1000
20 +
0.1CB
300
ns
Note 2
SDA and SCL fall time
TF
300
20 +
0.1CB
300
ns
Note 2
START condition hold time
THD:STA
4000
600
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
600
ns
Only relevant for
repeated START
condition
Data input hold time
THD:DAT
0—
ns
Data input setup time
TSU:DAT
250
100
ns
STOP condition setup time
TSU:STO
4000
600
ns
Output valid from clock
TAA
3500
900
ns
Note 1
Bus free time
TBUF
4700
1300
ns
Time the bus must be
free before a new
transmission can start
Output fall time from VIH
minimum to VIL maximum
TOF
250
20 +
0.1CB
250
ns
Note 2, CB
≤100 pF
Input filter spike suppression
(SDA and SCL pins)
TSP
N/A
0
50
ns
Note 3
Write cycle time
TWR
10
10
ms
Byte or Page mode
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: Not 100 percent tested. CB = total capacitance of one bus line in pF.
Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
AAAA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TBUF
TAA
TR
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