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參數(shù)資料
| 型號： | MULTILINK08UM |
| 英文描述： | MON08 Multilink Hardware Manual |
| 中文描述： | 的MON08多重硬件手冊 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 517K |
| 代理商： | MULTILINK08UM |
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22
MON08 Multilink User Manual
P&E
Microcomputer
Systems, Inc.
MON08 MULTILINK
PORTB1, PORTB2 and PORTB3 are used for entering monitor mode. By
default the user may directly bring these signals out to the target MON08
Header.
Alternatively, the user may pull up PORTB1 and pull down PORTB2, and pull
up/down PORTB3 for clock division. In which case the user does not need to
connect these signals to the target MON08 Header.
3.18
68HC908KX
Figure 3-18: 68HC908KX Family MON08 Pinout
The target GND is connected to the Pin 2 of the target MON08 Header.
The user must pull up the RESET line to target VDD with an external resistor.
The target IRQ line is directly connected to the Pin 6 of the target MON08
Header.
PORTA0 from the target processor is connected to the target MON08 Header
Pin 8, acting as the communications line. The MON08 MULTILINK pulls up
this signal with a 10K Ohm resistor to the target VDD.
PORTA1, PORTB0 and PORTB1 are used for entering monitor mode. By
default the user may directly bring these signals out to the target MON08
Header.
Alternatively, the user may pull up PORTB0 and pull down PORTA1 and
PORTB1. In which case the user does not need to connect these signals to the
target MON08 Header. The clock division is fixed Div 4.
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