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| 型號(hào)： | MULTILINK08UM |
| 英文描述： | MON08 Multilink Hardware Manual |
| 中文描述： | 的MON08多重硬件手冊(cè) |
| 文件頁(yè)數(shù)： | 28/52頁(yè) |
| 文件大?。?/td> | 517K |
| 代理商： | MULTILINK08UM |
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28
MON08 Multilink User Manual
P&E
Microcomputer
Systems, Inc.
MON08 MULTILINK
Alternatively, the user may pull up PORTB0 and pull down PORTB2. In which
case the user does not need to connect these signals to the target MON08
Header. The clock division is fixed Div 4.
3.26
68HC908RK
Figure 3-26: 68HC908RK Family MON08 Pinout
The target GND is connected to the Pin 2 of the target MON08 Header.
The target RESET line is directly connected to the Pin 4 of the target MON08
Header.
Alternatively, the user may pull up the RESET line to target VDD. In which
case the user does not need to connect this signal to the target MON08 Header.
The target IRQ line is directly connected to the Pin 6 of the target MON08
Header.
PORTA0 from the target processor is connected to the target MON08 Header
Pin 10, acting as the communications line. The MON08 MULTILINK pulls up
this signal with a 10K Ohm resistor to the target VDD.
PORTB0 and PORTB2 are used for entering monitor mode. By default the user
may directly bring these signals out to the target MON08 Header.
Alternatively, the user may pull up PORTB0 and pull down PORTB2. In which
case the user does not need to connect these signals to the target MON08
Header. The clock division is fixed Div 4.
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