MVTX2602
Data Sheet
109
Zarlink Semiconductor Inc.
14.0 BGA and Ball Signal Descriptions
14.1 BGA Views (Top-View)
14.1.1 Encapsulated view in unmanaged mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
A
B
C
D
E
F
G
H
J
K
L4
L7
L10
L13
L15
L4
LE0_
L8
L13
L16
L19
L33
L36
L39
L42
L45
LK0
LK0
RESE
OR4
OR1
SCL SDA
SBE
UT7
L1
L3
L6
L9
L12
L14
LA_A
LE1_
L7
L12
L15
L18
L32
L35
L38
L41
L44
LK1
LK1
L62
OR5
OR2
RESE
RESE
D0
UT8
UT3
LLK
L0
L2
L5
L8
L11
L3
LE_
LE_
DE1
L11
L14
L17
L20
L34
L37
L40
L43
LK2
LK2
P_D
TK0
OR3
OR0
AFD
TSTO
UT9
UT4
UT0
AD
L17
L19
L21
L23
L25
L27
L29
L31
L6
L10
LE0_
L49
L51
L53
L55
L57
L59
L61
L63
L47
COL
CLK
TSTO
TSTO
TSTO
TSTO
UT5
UT1
SCLK L16
L18
L20
L22
L24
L26
L28
L30
L5
L9
LE1_
L48
L50
L52
L54
L56
L58
L60
RESE
L46
LINK
TSTO
RESE
RESE
MOD
E
UT6
UT2
AC
N_
SEN
RESE
RESE
VCC
VCC
VCC
VCC
VCC
RESE
RESE
RESE
RESE
RESE
RESE
R_
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
VDD
VDD
VDD
VDD
RESE
RESE
RESE
RESE
RESE
L RVED
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
M
N
P
R
T
U
V
W
Y
A
A
A
B
A
C
RESE
RESE
RESE
RESE
RESE
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RVE
D
RESE
RD
RVE
D
RVE
D
RVE
D
VCC
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VCC
RVE
D
RESE
RD
RVE
D
RVE
D
RVE
D
RESE
RESE
RESE
RESE
RESE
RESE
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
RESE
MDIORVED
RESE
RESE
RESE
RESE
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
RESE
MDCMK
RESE
RESE
RESE
RESE
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
RESE
RESE
RESE
RESE
RESE
RESE
DE0
RESE
VCC
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VCC
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
VDD
VDD
VDD
VDD
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
RESE
RVED
M23_
CRS
M23_
RXD0
M23_
RXD1
A
D
A
E
AF
RESE
RESE
RESE
RESE
RESE
VCC
VCC
VCC
VCC
VCC
RESE
RESE
M23_
M23_
M23_
XEN
XD0
XD1
XD1
XEN
XD0
XD1
XEN
XD0
XD1
XEN
XD0
M10_
M10_
M10_
M13_
M16_
M15_
M16_
M15_
M15_
M18_
M18_
M18_
M20_
M20_
M20_
M22_
XD1
XD0
MRS
XD0
MRS
XD1
XD0
MRS
XD1
XD0
MRS
XD1
M10_
CRS
M10_
M13_
CRS
M13_
CRS
XD0
M15_
M17_
CRS
M18_
M20_
CRS
M20_
M22_
CRS
A
G
A
H
AJ
XEN
XD0
XD1
XD1
MRS
XD1
MRS
XD1
MRS
XD1
MRS
XD1
MRS
M11_
CRS
M12_
CRS
M14_
M15_
M16_
CRS
M18_
CRS
M19_
CRS
M21_
CRS
M22_
M22_
XD0
MRS
XD0
XD0
XD0
XD0
XD0
XD0
XD0
XD0
XD0
XD0
M11_
M11_
M12_
M12_
M14_
M14_
M13_
CRS
M17_
M17_
M19_
M19_
M21_
M21_
M22_
M1_R
XD1
M2_T
XEN
M2_R
XD1
M4_T
XEN
M4_R
XD1
M6_T
XEN
M6_R
XD1
M7_T
XEN
M7_R
XD1
M9_T
XEN
M9_R
XD1
M11_
TXEN
M11_
RXD1
M12_
TXEN
M12_
RXD1
M14_
TXEN
M14_
RXD1
M16_
TXEN
M13_
TXEN
M17_
TXEN
M17_
TXD1
M19_
TXEN
M19_
RXD1
M21_
TXEN
M21_
RXD1
1
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3
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5
6
7
8
9
10
11
12
13
14
15
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18
19
20
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