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參數(shù)資料
| 型號(hào)： | N01L1618N1AT-70I |
| 元件分類： | SRAM |
| 英文描述： | 64K X 16 STANDARD SRAM, 70 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 184K |
| 代理商： | N01L1618N1AT-70I |
(DOC# 14-02-009 REV G ECN# 01-0995)
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N01L1618N1A
AMI Semiconductor, Inc.
Functional Block Diagram
Functional Description
CE
WE
OE
UB
LB
I/O0 - I/O151
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
MODE
POWER
H
X
XXX
High Z
Standby2
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
Standby
L
X
H
High Z
Active
LL
X3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
L1
Data In
Write3
Active -> Standby4
LH
L
L1
Data Out
Read
Active -> Standby4
LH
H
L1
High Z
Active
Standby4
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any
external influence.
Capacitance1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
CIN
VIN = 0V, f = 1 MHz, TA = 25oC
8pF
I/O Capacitance
CI/O
VIN = 0V, f = 1 MHz, TA = 25oC
8pF
Address
Inputs
A0 - A3
Address
Inputs
A4 - A15
Word
Address
Decode
Logic
4K Page
x 16 word
x 16 bit
RAM Array
W
ord
Mux
Input/
Output
Mux
and
Buffers
Page
Address
Decode
Logic
Control
Logic
CE
WE
OE
UB
LB
I/O0 - I/O7
I/O8 - I/O15
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