參數(shù)資料
型號(hào): NAND01GW3B2AN6F
廠商: NUMONYX
元件分類(lèi): PROM
英文描述: 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48
封裝: 12 X 20 MM, LEAD FREE, PLASTIC, TSOP-48
文件頁(yè)數(shù): 11/64頁(yè)
文件大?。?/td> 632K
代理商: NAND01GW3B2AN6F
NAND01G-B, NAND02G-B
Bus operations
19/64
3.12
VSS Ground
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus Operations, for a summary.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
4.1
Command Input
Command Input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 23 and Table 24 for details of the timings requirements.
4.2
Address Input
Address Input bus operations are used to input the memory addresses. Four bus cycles are
required to input the addresses for 1Gb devices whereas five bus cycles are required for the
2Gb device (refer to Table 6 and Table 7, Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 24 and Table 24 for details of the timings requirements.
4.3
Data Input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 25 and Table 24 and Table 25 for details of the timings requirements.
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