參數(shù)資料
型號： NCP1611BDR2G
廠商： ON Semiconductor
文件頁數(shù)： 25/29頁
文件大?。?/td> 879K
描述： IC PFC CTLR HE ENHANCED 8-SOIC
標準包裝： 3,000
系列： *
NCP1611
http://onsemi.com
25
The output of the error amplifier is brought to pin 1 for
external loop compensation. Typically a type 2 network is
applied between pin1 and ground, to set the regulation
bandwidth below about 20 Hz and to provide a decent phase
boost.
The swing of the error amplifier output is limited within an
accurate range:
 It is forced above a voltage drop (V
F
) by some
circuitry.
 It is clamped not to exceed 4.0 V + the same V
F
voltage drop.
Hence, V
pin1
 features a 4 V voltage swing. V
pin1
 is then
offset down by (V
F
) and scaled down by a resistors divider
before it connects to the V
TON
 processing block and the
PWM section. Finally, the output of the regulation block is
a signal (V
REGUL
 of the block diagram) that varies
between 0 and a top value corresponding to the maximum
ontime.
The V
F
 value is 0.5 V typically.
(V
REGUL
)
max
V
REGUL
V
CONTROL
Figure 67. a) Regulation Block Figure (left), b) Correspondence Between V
CONTROL
 and V
REGUL
 (right)
Given the low bandwidth of the regulation loop, abrupt
variations of the load, may result in excessive over or
undershoot. Overshoot is limited by the OverVoltage
Protection connected to pin 8.
The NCP1611 embeds a dynamic response enhancer
circuitry (DRE) that contains undershoots. An internal
comparator monitors the feedback (V
pin8
) and when V
pin8
is lower than 95.5% of its nominal value, it connects a
200 mA current source to speedup the charge of the
compensation network. Effectively this appears as a 10x
increase in the loop gain.
In A version, DRE is disabled during the startup
sequence until the PFC stage has stabilized (that is when the
pfcOK signal of the block diagram, is high). The resulting
slow and gradual charge of the pin1 voltage (V
CONTROL
)
softens the soft startup sequence. In B version, DRE is
enabled during startup to speedup this phase and allow for
the use of smaller V
CC
 capacitors.
The circuit also detects overshoot and immediately
reduces the power delivery when the output voltage exceeds
105% of its desired level. The NCP1611 does not abruptly
interrupt the switching. Instead, the signal V
TON
  that
controls the ontime is gradually decreased by grounding
the V
REGUL
 signal applied to the V
TON
 processing block (see
Figure 66). Doing so, the ontime smoothly decays to zero
in four to five switching periods typically. If the output
voltage still increases, a second comparator immediately
disables the driver if the output voltage exceeds 107% of its
desired level.
The error amplifier OTA and the OVP, UVP and DRE
comparators share the same input information. Based on the
typical value of their parameters and if (V
out,nom
) is the
output voltage nominal value (e.g., 390 V), we can deduce:
 Output Regulation Level: V
out,nom
 Output UVP Level: V
out,uvp
 = 12% x V
out,nom
 Output DRE Level: V
out,dre
 = 95.5% x V
out,nom
 Output Soft OVP Level: V
out,sovp
 = 105% x V
out,nom
 Output Fast OVP level: V
out,fovp
 = 107% x V
out,nom
Current Sense and Zero Current Detection
The NCP1611 is designed to monitor the current flowing
through the power switch. A current sense resistor (R
sense
)
is inserted between the MOSFET source and ground to
generate a positive voltage proportional to the MOSFET
current (V
CS
). The V
CS
 voltage is compared to a 500 mV
internally reference. When V
CS
 exceeds this threshold, the
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