參數(shù)資料
型號(hào): NS7520B-1-I46
廠商: Digi International
文件頁(yè)數(shù): 10/68頁(yè)
文件大?。?/td> 0K
描述: IC ARM MICROPROCESSOR 177BGA
標(biāo)準(zhǔn)包裝: 160
系列: NET+ARM®
應(yīng)用: 網(wǎng)絡(luò)處理器
核心處理器: ARM7
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
RAM 容量: 外部
接口: EBI/EMI,以太網(wǎng),DMA,SPI,UART
輸入/輸出數(shù): 16
電源電壓: 1.4 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 177-LFBGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 177-BGA(13x13)
Ge ne r a l P u rp ose I / O
14
NS 75 20 Da ta shee t
03 /2 00 6
Notes:
1
RESET output indicates the reset state of the NS7520. PORTC4 persists beyond the negation of
RESET_ for approximately 512 clock cycles if the PLL is disabled. When the PLL is enabled,
PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds
times the ratio of the VCO to XTALA.
This GPIO is left in output mode active following a hardware RESET.
2
PORTC[3:0] pins provide level-sensitive interrupts. The inputs do not need to be synchronous
to any clock. The interrupt remains active until cleared by a change in the input signal level.
PORTC5
RTSB_
REJECT_
F15 U I/O
2
Channel 2 RTS_
CAM reject
PORTC41
RXCB/RIB_/
OUT1B_
RESET_
F12 U I/O
2
Pgm’able Out/
Channel 2
RXCLK/Channel 2
ring signal/
Channel 2 SPI
clock (CLK)
RESET output
PORTC32
RXDB
LIRQ3/
DACK2_
F13 U I/O
2
Channel 2 RXD
Level sensitive IRQ /
DMA channel 4/6
ACK
PORTC22
DSRB_
LIRQ2/RPSF_ E15 U I/O
2
Channel 2 DSR_
Level sensitive IRQ/
CAM request
PORTC12
CTSB_
LIRQ1/
DONE2_(O)
E12 U I/O
2
Channel 2 CTS_
Level sensitive IRQ /
DMA channel 4/6
DONE_Out
PORTC02
TXCB/
OUT2B_/
DCDB_
LIRQ0/
DONE2_(I)
E14 U I/O
2
Pgm’able Out/
Channel 2 DCD/
Channel 2 SPI
enable (SEL_)/
Channel 2 TXCLK
Level sensitive IRQ /
DMA channel 4/6
DONE_In
GPIO signal
Serial
signal
Other
signal
Pin
I/O
OD
Serial channel
description
Other
description
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