參數(shù)資料
型號(hào): NS7520B-1-I46
廠商: Digi International
文件頁(yè)數(shù): 13/68頁(yè)
文件大小: 0K
描述: IC ARM MICROPROCESSOR 177BGA
標(biāo)準(zhǔn)包裝: 160
系列: NET+ARM®
應(yīng)用: 網(wǎng)絡(luò)處理器
核心處理器: ARM7
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
RAM 容量: 外部
接口: EBI/EMI,以太網(wǎng),DMA,SPI,UART
輸入/輸出數(shù): 16
電源電壓: 1.4 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 177-LFBGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 177-BGA(13x13)
System mod e (test supp ort)
16
NS 75 20 Da ta shee t
03 /2 00 6
System mode (test support)
PLLTST_, BISTEN_, and SCANEN_ primary inputs control different test modes for both functional
and manufacturing test operations (see Table 3: "NS7520 test modes" on page 22).
JTAG test
JTAG boundary scan allows a tester to check the soldering of all signal pins and tri-state all
outputs.
ARM debugger signal descriptions
Symbol
Pin
I/O
OD
Description
PLLTST_
N15
I
Encoded with BISTEN_ and SCANEN_
Add an external pullup to 3.3V or pulldown to GND.
BISTEN_
M15
I
Encoded with PLLTST_ and SCANEN_
Add an external pullup to 3.3V or pulldown to GND.
SCANEN_
L13
I
Encoded with BISTEN_ and PLLTST_
Add an external pullup to 3.3V or pulldown to GND.
Symbol
Pin
I/O
OD
Description
TDI
N14 U
I
Test data in.
TDO
M13
O
2
Test data out.
TMS
M12 U
I
Test mode select.
TRST_
M14
I
Test mode reset.
Requires external termination when not being used (see
illustration of the termination circuit on the development
PCB).
TCK
P15
I
Test mode clock.
Add an external pullup to 3.3V.
Mnemonic
Signal
Description
TDI
Test data in
TDI operates the JTAG standard. Consult the JTAG specifications
for use in boundary-scan testing. These signals meet the
requirements of the Raven and Jeeni debuggers.
TDO
Test data out
TDO operates the JTAG standard. Consult the JTAG specifications
for use in boundary-scan testing. These signals meet the
requirements of the Raven and Jeeni debuggers.
TMS
Test mode select
TMS operates the JTAG standard. Consult the JTAG specifications
for use in boundary-scan testing. These signals meet the
requirements of the Raven and Jeeni debuggers.
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