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| 型號(hào)： | ORSO82G5-1FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 102/153頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
52
There is no way to tell where a cell starts unless one counts the cells from the beginning of the SPE. That means,
there is no way to regain lost cell delineation other than wait for the next SONET frame.
Cell Mode Transmit Path
In the transmit path in cell mode, the transmit logic creates a SONET-like transport frame for the data, adds the
required Transport OverHead bytes (cell mode automatically uses AUTO_TOH mode) and retimes the cell data
from the FPGA interface rate of 156 MHz to the framer rate of 77.76 MHz. The data are then sent to the SONET
logic blocks and SERDES. The Payload sub-block of the SONET logic operates somewhat differently than in
SONET mode, however.
Output Port Controller
The ORSO42G5 has two link controllers (OPC2s). In cell mode the Output Port Controller (OPC) is the block
responsible for directing trafc for the transmit trafc ow. There are four two-link controllers and one eight-link con-
troller (OPC8) in the ORSO82G5. The user provides 160-bit data (OPC8) or 40-bit data (OPC2s) at 156 MHz,
along with a cell valid strobe from the FPGA logic. No Link Header byte is sent with the cell data. The OPC provides
the following functions:
Accepts cell payload from the FPGA logic and assembles legal output cells from these.
Inserts Bit Interleaved Parity (BIP)
Schedules, manages and performs writes of cell data into TX FIFOs in the transmit framer blocks of all the eight-
links or up to 4 pairs of two-links.
Provides backpressure information to the FPGA to stop writes to the TXFIFO if the FIFO is not ready to accept
data.
The OPC blocks, shown in Figure 39, operate as follows:
OPC8 to stripe cells across eight links (ORSO82G5 only)
OPC2_A1 to service links AA,AB (ORSO82G5 only)
OPC2_A2 to service links AC,AD
OPC2_B1 to service links BA,BB (ORSO82G5 only)
OPC2_B2 to service links BC,BD
When operating with some links in the two-link cell mode, links not in an alignment group can optionally be oper-
ated in SONET and/or SERDES-only modes.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ORSO82G5-1FN680C1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1FN680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-2BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-2BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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