參數資料
型號： ORSO82G5-1FN680C
廠商： Lattice Semiconductor Corporation
文件頁數： 126/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
74
Table 17. Decoding of SCHAR_CHAN
The receive characterization test mode is entered when SCHAR_ENA=1 and SCHAR_TXSEL=0, In this mode,
one of the channels of SERDES outputs is observed at chip ports as shown in Table 18. The channel that is
observed is also based on the decoding of SCHAR_CHAN as shown in Table 18.
Table 18. SERDES Receive Characterization Mode
Embedded Core Block RAM
There are two independent memory slices (labeled A and B) in the embedded core. Each memory slice has a
capacity of 4K words by 36 bits. These are in addition to the block RAMs found in the FPGA portion of the
ORSO42G5 and ORSO82G5. Although the memory slices are in the embedded core part of the chip, they do not
interact with the rest of the embedded core circuits, but are standalone memories designed specically to increase
RAM capacity in the ORSO42G5 and ORSO82G5 chip. They can be used by the soft IP cores implemented in the
FPGA portion of the FPSC.
A block diagram of a memory slice is shown in Figure 48. Each memory slice is organized into two sections
(labeled SRAM A and SRAM B) and has one read port, one write port and four byte-write-enable (active-low) sig-
nals. Each byte has eight data bits and a control/parity bit. The control/parity bit responds to the same byte enable
(BYTEWN_x[x]) as it’s corresponding data. No special logic such as parity checking is performed on this bit by the
core. The read data from the memory is registered so that it works as a pipelined synchronous memory block. The
minimum timing specications are shown in Figure 49 and Figure 50. Signal names and functions are summarized
later in Table 19 and follow the general Series 4 naming conventions.
SCHAR_CHAN0
SCHAR_CHAN1
Channel
0
BA
1
0
BB
0
1
BC
1
BD
SERDES Output
Chip Port
LDOUTBx[9:0]
PSCHAR_LDIO[9:0]
RBC0Bx
PSCHAR_CKIO0
RBC1Bx
PSCHAR_CKIO1
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參數描述
ORSO82G5-1FN680C1 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1FN680I 功能描述:FPGA - 現場可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1FN680I1 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680C 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680I 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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