參數(shù)資料
型號： ORSO82G5-1FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 131/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
79
Table 22. SERDES Per-Channel Transmit Conguration Register Descriptions – ORSO42G5
Table 23. SERDES Per-Channel Receive Conguration Register Descriptions – ORSO42G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Transmit Per-Channel Conguration Registers (Read/Write) xx = [AC, AD, BC, BD]
30022 - AC
30032 - AD
30122 - BC
30132 - BD
[0]
TXHR_xx
00
Transmit Half Rate Selection Bit, Channel xx.
When TXHR_xx = 1, HDOUT_xx's baud rate =
(REFCLK[A:B]*8) and TCK78[A:B] =(REF-
CLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's
baud rate = (REFCLK[A:B]*16) and
TCK78[A:B]=(REFCLK[A:B]/2).
TXHR_xx = 0 on device reset.
Both
[1]
PWRDNT_xx
Transmit Powerdown Control Bit, Channel xx.
When PWRDNT_xx = 1, sections of the trans-
mit hardware are powered down.
PWRDNT_xx = 0 on device reset.
Both
[2]
PE0_xx
Transmit Preemphasis Selection Bit 0, Channel
xx. PE0_xx and PE1_xx select one of three pre-
emphasis settings for the transmit section.
PEO_xx=PE1_xx = 0, Preemphasis is 0%;
PEO_xx=1, PE1_xx = 0 or PEO_xx=0,
PE1_xx = 1, Preemphasis is 12.5%;
PEO_xx=PE1_xx = 1, Preemphasis is 25%.
PEO_xx=PE1_xx = 0 on device reset.
Both
[3]
PE1_xx
Both
[4]
HAMP_xx
Transmit Half Amplitude Selection Bit, Channel
xx. When HAMP_xx = 1, the transmit output
buffer voltage swing is limited to half its normal
amplitude. Otherwise, the transmit output buffer
maintains its full voltage swing.
HAMP_xx = 0 on device reset.
Both
[5:7]
RSVD
Reserved, Always set to “000”
—
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Receive Per-Channel Conguration Registers (Read/Write) xx = [AC, AD, BC, BD]
30023 - AC
30033 - AD
30122 - BC
30132 - BD
[0]
RXHR_xx
20
Receive Half Rate Selection Bit, Channel xx.
When RXHR_xx =1, HDIN_xx's baud rate =
(REFCLK[A:B]*8) and RCK78[A:B]=(REF-
CLK[A:B]/4); When RXHR_xx=0, HDIN_xx's
baud rate = (REFCLK[A:B]*16) and
RCK78[A:B]=(REFCLK/2).
RXHR_xx = 0 on device reset.
Both
[1]
PWRDNR_xx
Receiver Power Down Control Bit, Channel xx.
When PWRDNR_xx = 1, sections of the receive
hardware are powered down. PWRDNR_xx = 0
on device reset.
Both
[2:7]
RSVD
Reserved (Bit 2 = 1 on device reset)
—
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ORSO82G5-1FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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