參數(shù)資料
型號： ORSO82G5-1FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 108/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
58
Insuring group bundles are properly aligned.
Scheduling reads from the RX FIFOs. Cells are read one at a time from the congured links.
Parsing the cell data into payload data (along with selected header information). Cells which have errors that
make them unusable (such as BIP or sequence number errors) are thrown away. This dropping of errored cells
can be disabled through register bits CELL_BIP_INH_xx and CELL_SEQ_INX_xx.
Figure 44. IPC2 and IPC8 Block Diagrams
There are 5 IPC blocks in the embedded core. There is an IPC2 block for every channel pair:
IPC2_A1 combines links from channels AA,AB (ORSO82G5 only)
IPC2_A2 combines links from channels AC,AD
IPC2_B1 combines links from channels BA,BB (ORSO82G5 only)
IPC2_B2 combines links from channels BC,BD
The IPC8 block combines cells from all eight aligned links and transmits them to the FPGA logic (ORSO82G5
only).
Before an IPC can begin reading data from the Rx FIFOs and assembling cells, it must rst align all FIFOs in a port
bundle. This is accomplished by handshaking signals between the framer and the IPC. The framer indicates to the
IPC that framing has been acquired. The framer does not start lling the FIFOs, however, until the next A1/A2
SONET signal.
RX
FIFO
IPC2
Block
IPC2_[A:B][1:2][39:0]
SYSCLK156[A:B][1:2]
32
77.76 MHz
RX
FIFO
32
77.76 MHz
RX
FIFO
IPC8
IPC8[159:0]
SYSCLK156 8
32
77.76 MHz
RX
FIFO
32
77.76 MHz
LINK 0
LINK 1
LINK 0
LINK 7
40
160
FPGA
LOGIC
Block
FPGA
LOGIC
Cell
Extractor
Cell
Extractor
Cell
Extractor
Cell
Extractor
(ORSO82G5
only)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO82G5-1FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1FN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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