參數(shù)資料
型號： ORSO82G5-2F680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 119/153頁
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
68
Figure 47. ORSO42G5 and ORSO82G5 Clock Signals, Block A (High speed serial I/O also shown. Block B
has the same signals, SYSCLK156 8 is unique to the ORSO82G5 and common to both blocks).
REFCLKP_[A:B], REFCLKN_[A:B]: These are the differential reference clocks provided to the ORSO42G5 and
ORSO82G5 device as described earlier. They are used as the reference clock for both TX and RX paths. For oper-
ation of the serial links at 2.48 Gbps, the reference clocks will be at a frequency of 155.52 MHz.
RWCK[AA:BD]: These are the low-speed receive clocks from the embedded core to the FPGA across the core-
FPGA interface. These are derived from the recovered low-speed complementary clocks from the SERDES blocks.
RWCKAA belongs to Channel AA, RWCKAB belongs to channel AB and so on. With a reference clock input of
155.52 MHz, these clocks operate at 77.76 MHz.
RCK78[A:B]: These are muxed outputs of RWCKA[A:D] and RWCKB[B:D] respectively. With a reference clock
input of 155.52 MHz, these clocks operate at 77.76 MHz.
RSYSCLK[A:B][1:2]: These clocks are inputs to the SERDES block A and B respectively from the FPGA. These
are used by each channel as the read clock to read received data from the alignment FIFO within the embedded
core. Clocks RSYSCLKA[1:2] are used by channels in the SERDES block A and RSYSCLKB[1:2] by channels in
the SERDES block B. To guarantee that there is no overow in the alignment FIFO, it is an absolute requirement
that the write and read clocks be frequency locked within 0 ppm. Examples of how to achieve this are shown in the
later section on recommended board-level clocking.
FPGA
Logic
Common Logic,
Channel AA
(ORSO82G5 only)
Channel AB
(ORSO82G5 only)
Channel AD
Channel AC
RCK78A
TCK78A
RSYS_CLK_A1
TSYS_CLK_AA
RWCKAA
RWCKAB
TSYS_CLK_AB
RWCKAC
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_AD
RWCKAD
REFCLK[P:N]_A
2
HDIN[P:N]_AC
2
HDOUT[P:N]_AD
HDIN[P:N]_AD
2
HDOUT[P:N]_AC
HDOUT[P:N]_AB
2
HDIN[P:N]_AB
2
HDOUT[P:N]_AA
2
HDIN[P:N]_AA
2
Serial
Links
Cell Mode
All Modes
SONET Mode
TCK156A
TCK39A
TSYSCLK156 A1
SYSCLK156 8 (ORSO82G5 only)
TSYSCLK156 A2
Block A
RWCKAC
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相關代理商/技術參數(shù)
參數(shù)描述
ORSO82G5-2FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 2.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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