參數資料
型號： ORSO82G5-2F680I
廠商： Lattice Semiconductor Corporation
文件頁數： 71/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
24
Figure 10. Bit and Byte Alignment for DEMUX Block
SONET Mode Operation – Detailed Description
The following sections describe the data processing performed in the SONET logic blocks. The basic data ows in
the SONET Mode are shown in Figure 11. At a top level, the descriptions are separated into processing in the
transmit path (FPGA to serial link) and processing in the receive path (serial link to FPGA). In general, the descrip-
tions in the next sections are written to describe SONET mode operation, although some of the “SONET logic
blocks” are also used in cell mode operation. The various processing options are selected by setting bits in control
registers and status information is written to status registers. Both types of registers can be written and/or read
from the System Bus. Memory maps and descriptions for the registers are given in Table 21 through Table 36.
Figure 11. Basic Data Flows - SONET Mode
In the SONET mode, the transmit block receives 32-bit wide data from the FPGA (DINxx) on each of its channels
along with a frame pulse (DINxx_FP) per channel and a transmit clock (TSYCLKxx). Typically this will represent a
STS-48 stream on each link. The data are rst passed through a TOH block which will generate all the timing
pulses that are required to isolate individual overhead bytes (e.g., A1, A2, B1, D1-D3, etc.). The timing pulse gener-
Time
W
O
R
D
3
W
O
R
D
2
W
O
R
D
1
W
O
R
D
0
8:32
DEMUX
W
0
W
1
W
2
W
3
Bit and Byte alignment of
LDOUT[0:7] through the
8:32 DEMUX block
to the 32-bit 77MHz data bus
7
0
7
0
31
0
Pseudo-
SONET
Processing
User
I/O
Receive (RX) Path
Transmit (TX) Path
Cell
Processing
Pseudo-
SONET
Processing
Configurable
ORCA 4E04
FPGA Logic
MUX/DEMUX
and
SERDES
Configurable
as
four
or
eight
data
channels
organized
in
two
blocks
相關PDF資料
PDF描述
ORSO82G5-2F680C IC FPSC TRANSCEIVER 8CH 680-BGA
ORSO82G5-1F680I IC FPSC TRANSCEIVER 8CH 680-BGA
ORSO42G5-3BM484C IC FPSC TRANSCEIVER 4CH 484-BGA
ORSO42G5-2BM484I IC FPSC TRANSCEIVER 4CH 484-BGA
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相關代理商/技術參數
參數描述
ORSO82G5-2FN680C 功能描述:FPGA - 現場可編程門陣列 ORCA FPSC 1.5V 2.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680C1 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I 功能描述:FPGA - 現場可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I1 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3BM680C 功能描述:FPGA - 現場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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