參數(shù)資料
型號(hào)： ORSO82G5-2F680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 85/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
37
frame pulse, is less than the minimum threshold set by RX_FIFO_MIN. In the memory map section OOS is referred
to as SYNC2_[A2,B2]_OOS, SYNC4_OOS. OVFL is referred to as SYNC2_[A2,B2]_OVFL, SYNC4_OVFL.
Receive Clocking for Multi-channel Alignment – ORSO42G5
There are a total of seven clocks for the receive path, from FPGA to the core. The two used in SONET mode are
RSYSCLKA2 (for block A), and RSYSCLKB2 (for block B). The following diagrams show the recommended clock
distribution approaches for SONET mode multi-channel alignment modes. Cell mode alignment is discussed in the
section describing the Input Port Controller (IPC).)
SONET Mode Twin Alignment – ORSO42G5
Figure 22 describes the clocking scheme for twin alignment. In twin alignment, the valid channel pairs are AC,AD in
block A and BC,BD in block B. The gure provides the clocking scheme for block A as an example. RSYSCLKA2
should be sourced from RCK78A, RWCKAC or RWCKAD. For the ORSO42G5, the use of RCK78A is recom-
mended since it uses primary clock routing resources. This clocking approach provides the required 0 ppm clock
frequency matching for each pair and provides exibility in applications where the two pairs are received from asyn-
chronous sources.
Figure 22. Receive Clocking Diagram for Twin Alignment in Block A – ORSO42G5
SONET Mode Quad Alignment – ORSO42G5
Figure 23 shows the clocking scheme for four-channel alignment. In this application, both clocks RSYSCLKA2 and
RSYSCLKB2 should be sourced from a common clock. Either RCK78A or RCK78B can be used as a common
clock source. The gure shows RCK78A being used as the clock source.
SERDES
2.488 Gbps
DEMUX
RWCKAC (77.76 MHz)
FPGA
RWCKAD
RCK78A
Alignment
SPE
Generator
RSYSCLKA2
Framer,
Descrambler
Logic Common to Block
REFCLKA[P,N]
(155.52 MHz)
Channel AC
Channel AD
HDIN[P:N]_AC
SERDES
2.488 Gbps
HDIN[P:N]_AD
DEMUX
Alignment
SPE
Generator
Framer,
Descrambler
RWCKAD
FIFO
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO82G5-2FN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 2.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680C1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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