參數(shù)資料
型號： ORSO82G5-2F680I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 79/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
31
Figure 16. TX Frame Processor (TFP) Block Diagram
Payload Sub-block
The Payload sub block is activated by the cell mode frame pulse (cell mode) or DINxx_FP from FPGA (SONET
mode). A pulse on this signal indicates the start of a frame.
In SONET mode, only two types of data bytes are in each frame:
TOH bytes
SPE data bytes
There are N x 3 (N = 48) bytes of TOH per row and there are a total of 9 rows in a SONET frame. The rest of the
bytes in each row are SPE data bytes in SONET mode.
TOH Sub-block
This block is responsible formatting the 144 (48 x 3) bytes of TOH at the beginning of each row of the transport
frame. All TOH bytes may be transmitted transparently from the FPGA logic using the transparent mode. Alter-
nately, some or all TOH bytes may be inserted by the TOH block (AUTO_SOH and AUTO_TOH mode). The TOH
data is transferred across the FPGA/core interface as 32-bit words, hence 36 clock cycles (12 x 3) are needed to
transfer a TOH row. TOH insertion is controlled by software register bits as shown in the Register Map tables.
MUX
BLOCK
LDIN(7:0)
XCK311
PAYLOAD
BLOCK
TRANSPORT
OVERHEAD
BLOCK
SCRAMBLE
LOGIC
32-bit payload
scramble_disable
TX_FRM_PROC
SERDES INTERFACE
FPGA INTERFACE
(SONET MODE)
32-bit TOH data
Error
injection
controls
(control
register
bits)
Cell Mode
Frame Pulse
DINxy_FP
scramble_out (31:0)
DINxy[31:0] data
相關PDF資料
PDF描述
ORSO82G5-2F680C IC FPSC TRANSCEIVER 8CH 680-BGA
ORSO82G5-1F680I IC FPSC TRANSCEIVER 8CH 680-BGA
ORSO42G5-3BM484C IC FPSC TRANSCEIVER 4CH 484-BGA
ORSO42G5-2BM484I IC FPSC TRANSCEIVER 4CH 484-BGA
PIC32MX575F512L-80I/BG IC MCU 32BIT 512KB FLASH 121XBGA
相關代理商/技術參數(shù)
參數(shù)描述
ORSO82G5-2FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 2.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*