參數(shù)資料
型號： ORSO82G5-2FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 128/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
76
Figure 50. Minimum Timing Specs for Memory Blocks-Read Cycle (-1 Speed Grade)
Table 19 summarizes the Embedded Memory Signals at the Core/FPGA interface. In the table, an input refers to a
signal owing into the embedded core and an output refers to a signal owing out of the embedded core.
Table 19. Embedded Memory Core/FPGA Interface Signal Description
Register Maps
The memory map for the ORSO42G5 and ORSO82G5 core is only part of the full memory map of the ORSO42G5
and ORSO82G5 devices. The ORSO42G5 and ORSO82G5 are ORCA Series 4 based devices and thus use the
system bus as a communication bridge. The ORSO42G5 and ORSO82G5 core register map contained in this data
sheet only covers the embedded ASIC core of the device, not the entire device. The system bus itself, and the
generic FPGA memory map, are fully documented in the MPI/System Bus Application Note. As part of the system
bus, the embedded ASIC core of an FPSC is located at address offset 0x30000. The ORSO42G5 and ORSO82G5
embedded core is an eight-bit slave interface on the Series 4 system bus. The ORSO42G5 and ORSO82G5 core
registers are clocked by the system bus main clock.
Each ORCA device contains a device ID. This device ID is unique to each ORCA device and can be used for device
identication and assist in the system debugging. The device ID is located at absolute address 0x0-0x3. The
ORSO42G5 and ORCA82G5 device IDs are 0xDC012282. More information on the device ID and other Series 4
generic registers can be found in technical note TN1017, ORCA Series 4 MPI/System Bus.
If a clock is not provided to the reference clock, the registers will fail to operate.
FPGA/Embedded Core
Interface Signal Name]
Input (I) to
or Output (O)
from Core
Signal Description
Memory Slice Interface Signals
D_[A:B][35:0]
I
Data in – memory slice [A:B]
CKW_[A:B]
I
Write clock – memory slice [A:B].
CSWA_[A:B]
I
Write chip select for SRAM A – memory slice [A:B].
CSWB_[A:B]
I
Write chip select for SRAM B – memory slice [A:B].
AW_[A:B][10:0]
I
Write address – memory slice [A:B].
BYTEWN_[A:B][3:0]
I
Write control pins for byte-at-a-time write-memory slice [A:B].
Q_[A:B][35:0]
O
Data out – memory slice [A:B].
CKR_[A:B]
I
Read clock – memory slice [A:B].
CSR_[A:B]
I
Read chip select – memory slice [A:B]. CSR_[A:B]= 0 selects SRAM A.
CSR_[A:B]= 1 selects SRAM B.
AR_[A:B][10:0]
I
Read address – memory slice [A:B].
CKR
AR[10:0],
CSR
Q[35:0]
1.5 ns
4.5 ns
0.5 ns
2.0 ns
0 ns
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參數(shù)描述
ORSO82G5-2FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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