參數(shù)資料
型號： ORSO82G5-2FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 136/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
83
30823 - AC
30833 - AD
30923 - BC
30933 - BD
[0]
BYPASS_ALGN_FIFO_xx
00
Bypass alignment FIFO =1 in RX path in
SONET mode. DOUT_xx data is clocked off
RWCKxx.
SONET
[1]
SERDES_ONLY_MODE_xx
SERDES-Only Mode. SERDES_ONLY_MODE
=1 bypasses all the SONET and cell functions.
Data is sent directly from the SERDES to the
FPGA logic in the RX path and is passed
directly from the FPGA logic to the SERDES in
the TX path.
SERDES
Only
[2]
FORCE_B1_ERR_xx
Force B1 Error. FORCE_B1_ERR =1 forces a
Section B1 error (Bit Interleaved Parity Error) in
the TX path. Valid only when the corresponding
AUTO_TOH_xx bit or AUTO_B1_xx bit is set to
one.
Both
[3]
FORCE_BIP8_ERR_xx
Force BIP8 Error, FORCE_BIP8_ERR =1 forces
cell BIP8 error in the TX path.
Cell
[4]
FORCE_A1A2_ERR_xx
Force A1A2 Error, FORCE_A1A2_ERR =1
forces an error in A1A2 bytes (framing error) in
the TX path. Valid only when the corresponding
AUTO_TOH_xx bit or AUTO_A1A2_xx bit is set
to one.
Both
[5]
FORCE_EX_SEQ_ERR_xx
Force Excessive Sequence Errors.
FORCE_EXP_SEQ_ERR_xx = 1 forces
sequence errors in the TX path by inverting the
link header byte sequence number.
Cell
[6]
FORCE_SEQ_ERR_xx
Force Sequence Error, FORCE_SEQ_ERR =1
forces one sequence error in the TX path. After
this bit is set, the next Link Header byte’s
sequence number is inverted. The Link Header
after the errored Link Header byte will have the
correct sequence number
Cell
[7]
FORCE_RDI_xx
Force Remote Defect Indication, FORCE_RDI
=1 forces RDI errors in the TX path. The K2 byte
in TOH is set to “00000110. Valid only when
AUTO_TOH_xx bit is set to 1.
Cell
Table 26. Per-Channel Control Register Descriptions – ORSO42G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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參數(shù)描述
ORSO82G5-2FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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