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| 型號： | ORSO82G5-3FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 120/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
69
TCK156[A:B]: This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the 4
transmit SERDES clocks per block. There is one clock output per SERDES block. It is derived from REFCLK_[A:B]
and runs at the reference clock frequency.This clock is available from the core in all modes and used by the core in
cell mode.
TCK78[A:B]: This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the 4
transmit SERDES clocks per block. There is one clock output per SERDES block. It is derived from REFCLK_[A:B]
and runs at half the reference clock frequency. This clock is available from the core in all modes and used by the
core in SONET and SERDES-only mode.
TCK39[A:B]: This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the 4
transmit SERDES clocks per block. There is one clock output per SERDES block. It is derived from REFCLK_[A:B]
and runs at a quarter of the reference clock frequency. This clock is available from the core in all modes.
TSYSCLK[AA,…BD]: These clocks are inputs to the SERDES block A and B respectively from the FPGA. These
are used by each channel to control the timing of the Transmit Data Path in the SONET and SERDES-only modes.
(They are not used in cell mode.) To guarantee correct transmit operation theses clocks must be frequency locked
within 0 ppm to TCK78[A:B].
SYSCLK156 [A:B][1:2] and SYSCLK156 8: These clocks are inputs to the SERDES block A and B from the
FPGA. and are used by the cell processing blocks within the embedded core. Clocks SYSCLK156 A[1:2] are used
by channels in the SERDES block A and SYSCLK156 B[1:2] by channels in the SERDES block B for two-link cell
mode operation. SYSCLK156 8 is used by both blocks for eight-link cell mode in the ORSO82G5.
Sample Initialization Sequences – ORSO42G5
The following paragraphs show sample control register write sequences for initialization and resynchronization for
the major modes of the device. Hexadecimal values will be shown for the data to be written into the control regis-
ters. For these values bit 0 will be the MSb while bit 7 is the LSb. For the per-channel control registers, only the rst
register address is shown. The other per-channel control registers must also be initialized for the desired mode.
1. SERDES-Only Mode Initialization – ORSO42G5
Set SERDES Only mode (per channel, channel AA selected for sample initialization)
– 30823 and 30833
40
Set SERDES PLL to Lock to Data signal (per channel, channel AA selected for sample initialization)
– 30824 and 30834
80
Toggle SOFT_RESET once all clocks have stabilized
– 30A06
01
– 30A06
00
Provide a rising edge on the DINxx_START signal
2. SONET Mode Initialization – ORSO42G5
This sample initialization uses the alignment FIFO for two channel alignment and Auto_SOH mode
Set Dual Channel Alignment (per channel, channels AC and AD)
– 30822 and 30833
10
Set SERDES PLL to Lock to Data signal (per channel, channels AC and AD)
– 30824 and 30834
80
Set Auto_SOH Mode (per channel, channels AC and AD)
– 30826 and 30836
03
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| ORSPI4-1F1156I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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