參數(shù)資料
型號(hào)： ORSO82G5-3FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 63/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
17
Figure 3. Top Level Overview, TX Path Logic, Single Channel
Receiver Architecture
The receiver section receives high-speed serial data at the external differential CML input pins. These data are fed
to the clock recovery section which generates a recovered clock and retimes the data. Therefore the receive clocks
are asynchronous between channels. The data are then optionally framed, reformatted, aligned and passed to the
FPGA logic in various parallel data formats.
The top level receiver architecture is shown in Figure 4. The main logical blocks in the receive path are:
Receive SERDES and 8:32 DEMUX.
SONET processing logic.
Input Port Controllers (IPCs) which contain the cell processing logic.
Depending on the mode of operation, the FPGA to backplane data path may include or bypass the various logical
blocks.
FPGA Logic
Embedded Core
SONET
Scrambler
TOH
Block
TX
FIFO
32:8
MUX
OPC2/
OPC8
Payload
Block
Cell Processing
SONET Processing
600 Mb/s
- 2.7 Gb/s
SERDES
8
LDIN
xck311
1:8
Demux
Legend:
TCK39x
TCK78x
TCK156x
TSYSCLKx[A:D]
x = A for Block A, B for Block B
SYSCLK 156 8 (*ORSO82G5 only)
Line Key:
311MHz from
Other Links
in Block
77.76 MHz
SYSCLK156x[1:2]
TSYSCLKx[A:D]
TCK39x
TCK156x
TCK78X
REFCLK (155.52MHz)
nominal
Logic Common to Block
311MHz
SERDES-Only Mode
SONET Mode
Cell Mode
Cell/SONET or All Modes
Data
from
FPGA
or SYSCLK156 8*
Divide
by 2
Divide
by 2
Divide
by 2
Divide
by 4
SONET
Scrambler
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-G2-PAC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORSO82G5-FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓:
ORSPI4 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-1F1156C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSPI4-1F1156I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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