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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ORT82G5-2F680C
寤犲晢锛� Lattice Semiconductor Corporation
鏂囦欢闋佹暩(sh霉)锛� 4/119闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPSC TRANSCEIVER 8CH 680-BGA
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Product Discontinuation 01/Aug/2011
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� *
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
101
W18
鈥�
VSS
鈥�
V2
7 (CL)
5
IO
PL21D
A10/PPC_A24
L17C_A0
V3
7 (CL)
5
IO
PL21C
A9/PPC_A23
L17T_A0
W19
鈥�
VSS
鈥�
V4
7 (CL)
5
IO
PL21B
鈥�
L18C_A0
V5
7 (CL)
5
IO
PL21A
鈥�
L18T_A0
W4
7 (CL)
5
IO
PL22D
A8/PPC_A22
L19C_A0
W3
7 (CL)
5
IO
PL22C
VREF_7_05
L19T_A0
W1
7 (CL)
5
IO
PL22B
鈥�
L20C_A0
Y1
7 (CL)
5
IO
PL22A
鈥�
L20T_A0
Y2
7 (CL)
5
IO
PL23D
鈥�
L21C_D0
AA1
7 (CL)
5
IO
PL23C
鈥�
L21T_D0
Y13
鈥�
VSS
鈥�
Y4
7 (CL)
5
IO
PL23B
鈥�
L22C_A0
Y3
7 (CL)
5
IO
PL23A
鈥�
L22T_A0
Y5
7 (CL)
6
IO
PL24D
PLCK1C
L23C_A0
W5
7 (CL)
6
IO
PL24C
PLCK1T
L23T_A0
U3
7 (CL)
鈥�
VDDIO7
鈥�
AB1
7 (CL)
6
IO
PL24B
鈥�
L24C_D0
AA2
7 (CL)
6
IO
PL24A
鈥�
L24T_D0
AB2
7 (CL)
6
IO
PL25D
VREF_7_06
L25C_D0
AC1
7 (CL)
6
IO
PL25C
A7/PPC_A21
L25T_D0
Y14
鈥�
VSS
鈥�
AA4
7 (CL)
6
IO
PL25B
鈥�
AB4
7 (CL)
6
IO
PL26D
A6/PPC_A20
L26C_A0
AB3
7 (CL)
6
IO
PL26C
A5/PPC_A19
L26T_A0
W2
7 (CL)
鈥�
VDDIO7
鈥�
AD1
7 (CL)
7
IO
PL26B
鈥�
AE1
7 (CL)
7
IO
PL27D
WR_N/MPI_RW
L27C_D0
AD2
7 (CL)
7
IO
PL27C
VREF_7_07
L27T_D0
AC3
7 (CL)
7
IO
PL27B
鈥�
L28C_A0
AC4
7 (CL)
7
IO
PL27A
鈥�
L28T_A0
AF1
7 (CL)
8
IO
PL28D
A4/PPC_A18
L29C_D0
AE2
7 (CL)
8
IO
PL28C
VREF_7_08
L29T_D0
AB5
7 (CL)
8
IO
PL29D
A3/PPC_A17
L30C_A0
AA5
7 (CL)
8
IO
PL29C
A2/PPC_A16
L30T_A0
Y15
鈥�
VSS
鈥�
AD3
7 (CL)
8
IO
PL29B
鈥�
AG1
7 (CL)
8
IO
PL30D
A1/PPC_A15
L31C_D0
AF2
7 (CL)
8
IO
PL30C
A0/PPC_A14
L31T_D0
AD4
7 (CL)
8
IO
PL30B
鈥�
L32C_D0
AE3
7 (CL)
8
IO
PL30A
鈥�
L32T_D0
AD5
7 (CL)
8
IO
PL31D
DP0
L33C_A0
AC5
7 (CL)
8
IO
PL31C
DP1
L33T_A0
Table 45. ORT82G5 680-Pin PBGAM (fpBGA) Pinout (Continued)
680-PBGAM VDDIO Bank VREF Group
I/O
Pin Description
Additional Function
680-PBGAM
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
D38999/26JC8PN CONN PLUG 8POS STRAIGHT W/PINS
MS27467T25F61SC CONN PLUG 61POS STRAIGHT W/SCKT
31-320-RFX BNC PLUG, CRIMP RG-58
D38999/24JD19PN CONN RCPT 19POS JAM NUT W/PINS
D38999/20WG39SN CONN RCPT 39POS WALL MNT W/SCKT
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ORT82G5-2F680I 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
ORT82G5-2FN680C 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
ORT82G5-2FN680C1 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 10368 LUT 372 I/O RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
ORT82G5-2FN680I 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
ORT82G5-2FN680I1 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 10368 LUT 372 I/O RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256