- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄11731 > ORT82G5-2F680C (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 8CH 680-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ORT82G5-2F680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 72/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)當(dāng)前第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
56
Table 24. Decoding of SCHAR_CHAN
The receive characterization test mode is entered when SCHAR_ENA=1 and SCHAR_TXSEL=0, In this mode,
one of the channels of SERDES outputs is observed at chip ports as shown in Table 25. The channel that is
observed is also based on the decoding of SCHAR_CHAN as shown in Table 25.
Table 25. SERDES Receive Characterization Mode
Embedded Core Block RAM
There are two independent memory blocks (labeled A and B) built-into the Embedded ASIC Core (EAC). Each
memory block has a capacity of 4K words by 36 bits. These two memory blocks (also called “slices”) are in addition
to the block RAMs found in the FPGA portion of the ORT82G5.
Although the memory blocks/slices are in the EAC part of the chip, they do not interact with the rest of the EAC cir-
cuits, but are standalone memories designed specically to increase RAM capacity in the ORT82G5 chip. They can
be used by logic implemented in the FPGA portion of the FPSC. Figure 34 represents one of the two available
memory slices built into the EAC. The index “x” refers to the memory slice (x=A for slice A, x=B for slice B). Each
memory slice is organized into two sections, which are also labeled as A and B. In Figure 34, SDRAM A is one sec-
tion of slice x, and SDRAM B is another section of slice x. Data can be written to both sections of a slice indepen-
dently. However, a read access can access only one of sections A or B at any given time (CSR_x=0 selects section
A, CSR_x=1 selects section B).
The 36 bits written to or read from the memory slice are composed of 32 bits of data (bits 31:24, 23:16, 15:8, 7:0),
and 4 bits of parity (bits 35,34,33,32). The core performs no parity checking functions. The data read from the
memory is registered so that it works as a pipelined synchronous memory block.
For illustration purposes, assuming that the memory slice in Figure 34 is slice A (x=A), then certain signals apply to
both sections of slice A. These include D_A[35:0], CKW_A, AW_A[10:0], BYTEWN_A[3:0], Q_A[35:0], CKR_A,
CSR_A, and AR_A[10:0]. The BYTEWN_A[3:0] are byte and parity write enable bits for each byte and parity bit of
data being written.
BYTEWN_A[3] is associated with D_A[35,31:24].
BYTEWN_A[2] is associated with D_A[34,23:16].
BYTEWN_A[1] is associated with D_A[33,15:8].
BYTEWN_A[0] is associated with D_A[32,7:0].
The signals that are unique to each section of slice A are:
CSWA_A --enables writing to section A of slice A
CSWB_A -- enables writing to section B of slice A
SCHAR_CHAN0
SCHAR_CHAN1
Channel
0
BA
1
0
BB
0
1
BC
1
BD
SERDES Output
Chip Port
BYTSYNCBx
PSCHAR_BYTSYNC
WDSYNCBx
PSCHAR_WDSYNC
CVOBx
PSCHAR_CV
LDOUTBx[9:0]
PSCHAR_LDIO[9:0]
RBC0Bx
PSCHAR_CKIO0
RBC1Bx
PSCHAR_CKIO1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| D38999/26JC8PN | CONN PLUG 8POS STRAIGHT W/PINS |
| MS27467T25F61SC | CONN PLUG 61POS STRAIGHT W/SCKT |
| 31-320-RFX | BNC PLUG, CRIMP RG-58 |
| D38999/24JD19PN | CONN RCPT 19POS JAM NUT W/PINS |
| D38999/20WG39SN | CONN RCPT 39POS WALL MNT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-2F680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2FN680C1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2FN680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。