- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄11733 > ORT82G5-2FN680C (Lattice Semiconductor Corporation)IC TRANCEIVERS FPSC 680FPBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ORT82G5-2FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 25/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)當(dāng)前第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
13
Dual Port RAMs
In addition to the backplane interface blocks, there are two independent memory blocks in the ASB. Each memory
block has a capacity of 4k words by 36 bits. It has one read port, one write port, and four byte-write-enable (active-
low) signals. The read data from the memory block is registered so that it works as a pipelined synchronous mem-
ory block.
FPSC Conguration
Conguration of the ORT42G5 and ORT82G5 occurs in two stages: FPGA bitstream conguration and embedded
core setup.
Prior to becoming operational, the FPGA goes through a sequence of states, including power up, initialization, con-
guration, start-up, and operation. The FPGA logic is congured by standard FPGA bit stream conguration means
as discussed in the Series 4 FPGA data sheet.
After the FPGA conguration is complete, the options for the embedded core are set based on the contents of reg-
isters that are accessed through the FPGA system bus.
The system bus itself can be driven by an external PowerPC compliant microprocessor via the MPI block or via a
user master interface in FPGA logic. A simple IP block that drives the system by using the user register interface
and very little FPGA logic is available in the MPI/System Bus Technical Note. This IP block sets up the embedded
core via a state machine and allows the ORT42G5 and ORT82G5 to work in an independent system without an
external microprocessor interface.
Backplane Transceiver Core Detailed Description
The following sections describe the various logic blocks in the Embedded Core portion of the FPSC. The FPGA
section of the FPSC is identical to an ORCA OR4E04 FPGA except that the pads on one edge of the FPGA chip
are replaced by the Embedded Core. For a detailed description of the programmable logic functions, please see
the ORCA Series 4 FPGA Data Sheet and related application and technical notes.
The major functional blocks in the Embedded Core include:
Two SERializer-DESerializer (SERDES) blocks and Clock and Data Recovery (CDR) circuitry
8b/10b encoder/decoders
Transmit pre-emphasis circuitry
4-to-1 multiplexers (MUX) and 1-to-4 demultiplexers (DEMUX)
Fibre channel synchronization state machine
XAUI link alignment state machine
Alignment FIFOs
Embedded 4K x 36 RAM blocks (independent from transceiver logic).
A top level block diagram of the Embedded Core Logic is shown in Figure 2. The Embedded RAM blocks are not
shown. The external pins for the Embedded Core are listed later in this data sheet in Table 41 and the signals at the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSP430F4793IPZ | IC MCU 16BIT 60KB FLASH 100LQFP |
| VE-J4B-IW-F3 | CONVERTER MOD DC/DC 95V 100W |
| PIC18F4510-I/ML | IC MCU FLASH 16KX16 44QFN |
| VE-J4B-IW-F2 | CONVERTER MOD DC/DC 95V 100W |
| PIC32MX675F256L-80I/PF | IC MCU 32BIT 256KB FLASH 100TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-2FN680C1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2FN680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C2 | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。