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| 型號： | ORT82G5-2FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 33/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
20
Figure 6. Basic Logic Blocks, Receive Path, Single Channel (Typical Reference Clock Frequency)
Each channel provides its own received clock, received data and K-character detect signals to the FPGA logic.
Incoming data from multiple channels can be aligned using comma (/K/) characters or /A/ character (as specied
either in Fibre Channel specications or in IEEE 802.3ae for XAUI based interfaces). If the 8b/10b decoders are
bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in this
8b/10b bypass mode.
Detailed descriptions of data synchronization, of the SERDES, DEMUX and Multi-Channel Alignment blocks and of
the Fibre Channel and XAUI state machines are given in following sections. Receive clock distribution is described
in a later section of this data sheet.
Synchronization
The SERDES RX logic performs four levels of synchronization on the incoming serial data stream. Each level
builds upon the previous, providing rst bit, then byte (character), then channel (32-bit word), and nally multi-chan-
nel alignment. Each step is described functionally in the following paragraphs. The details of the logical implemen-
tations are described in subsequent sections.
Bit alignment is the task of the Clock/Data Recovery (CDR) block. This block utilizes a PLL that locks to the transi-
tions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. If the PLL
is unable to lock to the serial data stream, it instead locks to REFCLK[A:B] to stabilize the voltage-controlled oscil-
lator (VCO), and periodically switches back to the serial data stream to again attempt synchronization. This pro-
cess continues until a valid input data stream is detected and lock is achieved. The CDR can maintain lock on data
as long as the input data stream contains an adequate data “eye” (i.e., jitter is within specication) and the maxi-
mum data stream run length is not exceeded.
REFCLKP_[A:B]
REFCLKN_[A:B]
REFCLK
Buffer
MUX
RCK78[A:B]
78.125 MHz
RCKSEL[0:1][A:B]
Logic Common to Block
From other channel
or channels
To other
channel or
channels
From Control
Register
{
PLL
CML
Buffer
1:10
DEMUX
8B/10B
Encoder
(with
bypass)
HDINP_xx
HDIN_xx
CDR
Byte
Align
RX SERDES Block
XAUI
State
Machine
1:4
DEMUX
(x 10)
156.25 MHz
FIFO
Multi-
Channel
Alignment
FPGA
Logic
Backplane
Serial
Link
RWCKxx
78.125 MHz
Multi-Channel
Alignment Block
78.125 MHz
78.125 MHz Clock
RALIGNxx[3:0]
Align Character Detect
4
RWBIT8xx[3:0]
4 bits k-control
32
RWDxx[31:0]
32-bit data
RSYS_CLK_x#
78.125 MHz
2:1
MUX
(x40)
MRWDxx[39:0]
CV_SELxx
4
RWBIT9xx[3:0]
40
36
32-bit data
4 bits k-ctrl
Synchronization
Status bits
See Table 8
Fibre Channel State
Machine
SRBD_xx[0:9]
DEMUX
Block
SCVxx
312.5 MHz
Clocks
10
2
SBYTSYNC_xx
SWDSYNC_xx
For ORT42G5:
xx = [AC, AD, BC, BD]
x# = [A2, B2]
For ORT82G5:
xx = [AA, AB, ... BD]
x# = [A1, ...B2]
3
FPGA
Logic
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-2FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2FN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-2FN680I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-3BM680C2 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs |
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