參數(shù)資料
型號(hào): ORT82G5-2FN680C
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 49/119頁(yè)
文件大?。?/td> 0K
描述: IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告: Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝: 24
系列: *
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)當(dāng)前第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
35
Table 9. Denition of Status Bits of MRWDxx that Vary for Different Channels for the ORT42G5
In the ORT42G5, SYNC2_[A, B]_OOS and SYNC4_OOS signals can be used with CH24_SYNC_xx to determine
if the desired multi-channel alignment was successful. If, when CH24_SYNC_xx goes high with the corresponding
OOS signal remaining low, the data being transferred across the core/FPGA interface is correctly aligned between
channels. Note that only the signals corresponding to the selected alignment mode will be meaningful.
12
bit 2 of 10-bit data 1
bit 2 of byte 1
11
bit 1 of 10-bit data 1
bit 1 of byte 1
10
bit 0 of 10-bit data 1
bit 0 of byte 1
09
bit 9 of 10-bit data 0
CV_xx0, code violation, byte 0
VL (connected to ground)
08
bit 8 of 10-bit data 0
K_CTRL for byte 0
07
bit 7 of 10-bit data 0
bit 7 of byte 0
06
bit 6 of 10-bit data 0
bit 6 of byte 0
05
bit 5 of 10-bit data 0
bit 5 of byte 0
04
bit 4 of 10-bit data 0
bit 4 of byte 0
03
bit 3 of 10-bit data 0
bit 3 of byte 0
02
bit 2 of 10-bit data 0
bit 2 of byte 0
01
bit 1 of 10-bit data 0
bit 1 of byte 0
00
bit 0 of 10-bit data 0
bit 0 of byte 0
Channel
Index
Bit Index
Name
Description
all
39
CH24_SYNCxx
Multi-channel alignment attempt complete if 1
AC
29
CV_AC_OR
Code violation in one or more of the received 10-bit groups for channel AC
AC
19
SYNC2_A_OOS
Dual channel synchronization of channels AC and AD not successful if 1
AD
29
CV_AD_OR
Code violation in one or more of the received 10-bit groups for channel AD
AD
19
SYNC4_OOS
Four channel synchronization not successful if 1
BC
29
CV_BC_OR
Code violation in one or more of the received 10-bit groups for channel BC
BC
19
SYNC2_B_OOS
Dual channel synchronization of channels BC and BD not successful if 1
BD
29
CV_BD_OR
Code violation in one or more of the received 10-bit groups for channel BD
BD
19
SYNC4_OOS
Eight channel synchronization not successful if 1
Table 10. Denition of Status Bits of MRWDxx that Vary for Different Channels for the ORT82G5
Channel
Index
Bit Index
Name
Description
all
39
CH248_SYNCxx
Multi-channel alignment attempt complete if 1
AA
29
CV_AA_OR
Code violation in one or more of the received 10-bit groups for channel AA
AA
19
SYNC2_A1_OOS
Dual channel synchronization of channels AA and AB not successful if 1
AB
29
CV_AB_OR
Code violation in one or more of the received 10-bit groups for channel AB
AB
19
SYNC4_A_OOS
Quad channel synchronization of SERDES quad A not successful if 1
AC
29
CV_AC_OR
Code violation in one or more of the received 10-bit groups for channel AC
AC
19
SYNC2_A2_OOS
Dual channel synchronization of channels AC and AD not successful if 1
AD
29
CV_AD_OR
Code violation in one or more of the received 10-bit groups for channel AD
AD
19
SYNC8_OOS
Eight channel synchronization not successful if 1
Table 8. Denition of Bits of MRWDxx[39:0] (Continued)
Bit Index
8b10bR=0
8b10bR=1
NOCHALGN[A:B]=1
CV_SELxx=0
NOCHALGN[A:B]=1
CV_SELxx=1
NOCHALGN[A:B]=0
CV_SELxx=1
相關(guān)PDF資料
PDF描述
MSP430F4793IPZ IC MCU 16BIT 60KB FLASH 100LQFP
VE-J4B-IW-F3 CONVERTER MOD DC/DC 95V 100W
PIC18F4510-I/ML IC MCU FLASH 16KX16 44QFN
VE-J4B-IW-F2 CONVERTER MOD DC/DC 95V 100W
PIC32MX675F256L-80I/PF IC MCU 32BIT 256KB FLASH 100TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT82G5-2FN680C1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2FN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3BM680C2 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs