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參數(shù)資料
| 型號： | ORT82G5 |
| 英文描述： | ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進文化基金 |
| 文件頁數(shù)： | 26/92頁 |
| 文件大?。?/td> | 1823K |
| 代理商： | ORT82G5 |
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26
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Backplane Transceiver Core Detailed
Description
(continued)
Receive Path (Backplane
→
FPGA)
The deMUX has to accumulate four sets of characters
presented to it at the SERDES receive interface and
put these out at one time at the low-speed receive
interface.
Another task of the deMUX is to recognize the synchro-
nizing event and adjust the 4-byte boundary so that the
synchronizing character leads off a new 4-byte word.
This feature will be referred to as word alignment in
other areas of this document. Word alignment will only
occur when the communication channel is synchro-
nized. When there is no synchronization of the link, the
deMUX will continue to output 4-byte words at some
arbitrary, but constant, boundary.
The deMUX passes on to the channel alignment FIFO
block a set of control signals that indicate the location
of the synchronizing event. RCOMMAx[3:0] are these
indicators. If there is no link synchronization, all of the
RCOMMAx[3:0] bits will be 0s independent of synchro-
nizing events that come in. When the link is synchro-
nized, then the bit that corresponds to the time of the
synchronization event will be set to a 1.
The relationship between a time sequence of values
input at SRBDx[7:0] to the values output at RWDx[31:0]
is shown in Figure 9 below. A parallel relationship
exists between SRBDx[8] and RWBIT8x[3:0] as well as
between SRBDx[9] and RWBIT9x[3:0].
2268(F)
Figure 9. Receive DeMUX Block for a Single SERDES Channel
8
E
PLL & CDR
1:4
DEMUX
(X 10)
XAUI LINK
STATE
MACHINE
SRBDx[9:0]
SBYTSYNCx
SRBC0x
SCVx
RWCKx
RCOMMAx[3:0]
RWBIT8x[3:0]
RWBIT9x[3:0]
SERDES
BLOCK
DEMUX
BLOCK
SWDSYNCx
SRBC1x
p
q
r
s
t
x
y
z
SRBDx[7:0]
10-bit
RWDx[31:0]
p7-0q7-0r7-0s7-0
t7-0x7-0y7-0z7-0
p8
s8
q8
r8
t8
z8
x8
y8
p9
s9
q9
r9
t9
z9
x9
y9
pc
sc
qc
rc
tc
zc
xc
yc
p
q
r
s
t
x
y
z
40-bit
RWDx[31:24]
RWDx[23:16]
RWDx[15:8]
RWDx[7:0]
LATENCY = 4 RWCKx CLOCKS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1F680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-1FN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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