參數(shù)資料
型號： ORT82G5
英文描述： ORCA ORT82G5 1.0.1-25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： ORCA的ORT82G5 1.0.1-25/2.0-2.5/3.125 Gb /秒背板接口促進文化基金
文件頁數(shù)： 38/92頁
文件大?。?/td> 1823K
代理商： ORT82G5
38
Agere Systems Inc.
Preliminary Data Sheet
July 2001
1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface
ORCA
ORT82G5 FPSC Eight-Channel
Memory Map
(continued)
Table 12. Memory Map
(continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES A Transmit Channel Configuration Registers
30002
TXHR_AA
Transmit Half
Rate Selec-
tion Bit, Bank
A, Channel A.
When TXHR =
1, the trans-
mitter sam-
ples data on
the falling
edge of the
TBC clock.
When TXHR =
0, the trans-
mitter sam-
ples data on
the falling
edge of the
double rate
clock (derived
from TBC).
TXHR = 0 on
device reset.
TXHR_AB
Transmit Half
Rate Selec-
tion Bit, Bank
A, Channel B.
When TXHR =
1, the trans-
mitter sam-
ples data on
the falling
edge of the
TBC clock.
When TXHR =
0, the trans-
mitter sam-
ples data on
the falling
edge of the
double rate
clock (derived
from TBC).
TXHR = 0 on
device reset.
TXHR_AC
Transmit Half
Rate Selec-
tion Bit, Bank
A, Channel C.
When TXHR =
1, the trans-
mitter sam-
ples data on
the falling
edge of the
TBC clock.
When TXHR =
0, the trans-
mitter sam-
ples data on
the falling
edge of the
double rate
clock (derived
from TBC).
TXHR = 0 on
device reset.
PWRDNT_AA
Transmit Pow-
erdown Con-
trol Bit, Bank
A, Channel A.
When
PWRDNT = 1,
sections of the
transmit hard-
ware are pow-
ered down to
conserve
power.
PWRDNT = 0
on device
reset.
PE0_AA
Transmit Pre-
emphasis
Selection Bit
0, Bank A,
Channel A.
PE0, together
with PE1,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE0 = 0
on device
reset.
PE1_AA
Transmit Pre-
emphasis
Selection Bit
1, Bank A,
Channel A.
PE1, together
with PE0,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE1 = 0
on device
reset.
HAMP_AA
Transmit Half
Amplitude
Selection Bit,
Bank A, Chan-
nel A. When
HAMP = 1, the
transmit out-
put buffer volt-
age swing is
limited to half
its amplitude.
Otherwise, the
transmit out-
put buffer
maintains its
full voltage
swing. HAMP
= 0 on device
reset.
TBCKSEL_AA
Transmit Byte
Clock Selec-
tion Bit, Bank
A, Channel A.
When TBCK-
SEL = 0, the
internal XCK
is selected.
Otherwise, the
TBC clock is
selected.
TBCKSEL = 0
on device ser-
set.
RINGOVR_AA
Transmit Ring
Counter Bub-
ble Detector
Alarm Over-
ride Control
Bit, Bank A,
Channel A.
When RIN-
GOVR = 0, the
bubble detec-
tor alarm is
effective. Oth-
erwise, the
bubble detec-
tor alarm is not
effective. RIN-
GOVR = 0 on
device reset.
8B10BT_AA
Transmit 8B/
10B Encoder
Enable Bit,
Bank A, Chan-
nel A. When
8B10BT = 1,
the 8B/10B
encoder on
the transmit
path is
enabled. Oth-
erwise, it is
bypassed.
8B10BT = 0
on device
reset.
00
30012
PWRDNT_AB
Transmit Pow-
erdown Con-
trol Bit, Bank
A, Channel B.
When
PWRDNT = 1,
sections of the
transmit hard-
ware are pow-
ered down to
conserve
power.
PWRDNT = 0
on device
reset.
PE0_AB
Transmit Pre-
emphasis
Selection Bit
0, Bank A,
Channel B.
PE0, together
with PE1,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE0 = 0
on device
reset.
PE1_AB
Transmit Pre-
emphasis
Selection Bit
1, Bank A,
Channel B.
PE1, together
with PE0,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE1 = 0
on device
reset.
HAMP_AB
Transmit Half
Amplitude
Selection Bit,
Bank A, Chan-
nel B. When
HAMP = 1, the
transmit out-
put buffer volt-
age swing is
limited to half
its amplitude.
Otherwise, the
transmit out-
put buffer
maintains its
full voltage
swing. HAMP
= 0 on device
reset.
TBCKSEL_AB
Transmit Byte
Clock Selec-
tion Bit, Bank
A, Channel B.
When TBCK-
SEL = 0, the
internal XCK
is selected.
Otherwise, the
TBC clock is
selected.
TBCKSEL = 0
on device ser-
set.
RINGOVR_AB
Transmit Ring
Counter Bub-
ble Detector
Alarm Over-
ride Control
Bit, Bank A,
Channel B.
When RIN-
GOVR = 0, the
bubble detec-
tor alarm is
effective. Oth-
erwise, the
bubble detec-
tor alarm is not
effective. RIN-
GOVR = 0 on
device reset.
8B10BT_AB
Transmit 8B/
10B Encoder
Enable Bit,
Bank A, Chan-
nel B. When
8B10BT = 1,
the 8B/10B
encoder on
the transmit
path is
enabled. Oth-
erwise, it is
bypassed.
8B10BT = 0
on device
reset.
00
30022
PWRDNT_AC
Transmit Pow-
erdown Con-
trol Bit, Bank
A, Channel C.
When
PWRDNT = 1,
sections of the
transmit hard-
ware are pow-
ered down to
conserve
power.
PWRDNT = 0
on device
reset.
PE0_AC
Transmit Pre-
emphasis
Selection Bit
0, Bank A,
Channel C.
PE0, together
with PE1,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE0 = 0
on device
reset.
PE1_AC
Transmit Pre-
emphasis
Selection Bit
1, Bank A,
Channel C.
PE1, together
with PE0,
selects one of
three preem-
phasis set-
tings for the
transmit sec-
tion. PE1 = 0
on device
reset.
HAMP_AC
Transmit Half
Amplitude
Selection Bit,
Bank A, Chan-
nel C. When
HAMP = 1, the
transmit out-
put buffer volt-
age swing is
limited to half
its amplitude.
Otherwise, the
transmit out-
put buffer
maintains its
full voltage
swing. HAMP
= 0 on device
reset.
TBCKSEL_AC
Transmit Byte
Clock Selec-
tion Bit, Bank
A, Channel C.
When TBCK-
SEL = 0, the
internal XCK
is selected.
Otherwise, the
TBC clock is
selected.
TBCKSEL = 0
on device ser-
set.
RINGOVR_AC
Transmit Ring
Counter Bub-
ble Detector
Alarm Over-
ride Control
Bit, Bank A,
Channel C.
When RIN-
GOVR = 0, the
bubble detec-
tor alarm is
effective. Oth-
erwise, the
bubble detec-
tor alarm is not
effective. RIN-
GOVR = 0 on
device reset.
8B10BT_AC
Transmit 8B/
10B Encoder
Enable Bit,
Bank A, Chan-
nel C. When
8B10BT = 1,
the 8B/10B
encoder on
the transmit
path is
enabled. Oth-
erwise, it is
bypassed.
8B10BT = 0
on device
reset.
00
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