參數(shù)資料
型號(hào)： OX16PCI952
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
中文描述： 集成高性能的雙UART，并行端口和5.0V PCI接口
文件頁(yè)數(shù)： 17/76頁(yè)
文件大小： 1386K
代理商： OX16PCI952
DataSheet Revision 1.1
Page 17
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
6.3
Accessing Function 0 and Function 1
Access to the internal UARTs and the Parallel Port is achieved (at addresses defined by the Base Address Registers in the PCI
configuration space) via standard I/O and memory mapping. These BARs are configured by the systemto allocate blocks of I/O
and memory space to the logical functions, according to the size required by the function. The base addresses that have been
allocated can then be used to access the functions. The mapping of these BARs is shown inTable 6.
BAR
Function 0
0
Internal UART 0 (I/O Mapped)
1
Internal UART 1 (I/O Mapped)
2
Local configuration registers (I/O Mapped)
3
Local configuration registers (Memory Mapped)
4
Internal UART 0 and UART 1 (Memory Mapped)
5
Not Implemented
Function 1
1
Parallel Port Base Registers (I/O Mapped)
Parallel Port Extended Registers (I/O Mapped)
Not Implemented
Table 6: Base Address Register definition
NOTE 1. Function 1 is only accessible in the Dual Function mode (MODE0 = ‘0’)
6.3.1
IO and memory space
BAR 0, BAR 1, and BAR 4 of function 0 are used to access
the internal UARTs through I/O and Memory transactions.
The function reserves 8-byte blocks of I/O space for each
UART (total of 16-bytes) and a 4K byte block of memory
space for both UARTs.
Once the I/O and/or the Memory access enable bits in the
Command register (of this functions PCI configuration
space) are set, the internal UARTs can be accessed using
the mappings shown in the following tables.
UART 0
Address
for UART 0 in I/O space
000
001
002
003
004
005
006
007
UART 1
Address
for UART 1 in I/O space
000
001
002
003
004
005
006
007
Base Address mapping for UART0 and UART 1 registers,
for I/O accesses.
PCI access to the internal UARTs
PCI Offset from Base Address 0 ,
00
01
02
03
04
05
06
07
PCI Offset from Base Address 1,
00
01
02
03
04
05
06
07
UART
Address
000
001
002
003
004
005
006
007
PCI Offset from Base Address 4, for
UART0 and UART 1 in Memory space (hex)
UART 0
00
04
08
0C
10
14
18
1C
UART 1
20
24
28
2C
30
34
38
3C
Base Address mapping for UART 0 and UART1 registers,
for memory accesses
Note 1:
Since 4K of memory space is reserved to map both
UARTs and the full bus address is not used for decoding, there are a
number of aliases of the UARTs in the allocated memory region
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