參數(shù)資料
型號(hào): OX16PCI952
廠商: Electronic Theatre Controls, Inc.
英文描述: Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
中文描述: 集成高性能的雙UART,并行端口和5.0V PCI接口
文件頁(yè)數(shù): 71/76頁(yè)
文件大小: 1386K
代理商: OX16PCI952
DataSheet Revision 1.1
Page 71
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
Read from EPP Address Register (EPP Read Address cycle)
PCI CLK no (1
st
Transaction)
1
4
8
8-9
12
15-16
- Start of PCI Read fromEPP Address register
- Start of EPP address read cycle on parallel port side.
- PCI transaction completes with a ‘retry’ (without affecting current EPP read address cycle) as EPP cycle cannot complete within 16 PCI CLK cycles
- Peripheral Asserts BUSY in response to the host driving SLIN_N low.
- Host responds to BUSY by de-asserting SLIN_N (3 clock cycles after sampling BUSY)
- Peripheral Deasserts BUSY
- EPP cycle completed.
PCI CLK no (Retry Transaction)
1
5
Tslin (PCI clk to valid SLIN_N)
Tpd (PCI clk to valid Port Address) - 16ns max*
EPP Read Address Cycle duration is dependant upon the timng response of the peripheral’s BUSY line and the parallel port
filters. Example waveformhas the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the
host to the peripheral’s BUSY line when the filters are enabled.
*These values exclude the effects of external parasitic (board) capacitances.
- Start of Retry transaction, to the original read fromEPP address register
- Retry transaction completes with “Data Transfer”, without initiating another EPP read address cycle.
- 16ns max*
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