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參數(shù)資料
| 型號： | P28F010-120 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 1024K (128K x 8) CMOS FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 120 ns, PDIP32 |
| 封裝： | 0.620 X 1.640 INCH, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 6/30頁 |
| 文件大?。?/td> | 405K |
| 代理商： | P28F010-120 |
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28F010
290207–4
Figure 4. 28F010 in a 80C186 System
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F010 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power sup-
plies during erasure and programming; and maxi-
mum EPROM compatibility.
In the absence of high voltage on the V
PP
pin, the
28F010 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelli-
gent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is ap-
plied to the V
PP
pin. In addition, high voltage on V
PP
enables erasure and programming of the device. All
functions associated with altering memory con-
tentsDIntelligent Identifier, erase, erase verify, pro-
gram, and program verifyDare accessed via the
command register.
Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or out-
put data for erase and program verification.
Integrated Stop Timer
Successive command write cycles define the dura-
tions of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simpli-
fied timing control over these operations; thus elimi-
nating the need for maximum program/erase timing
specifications. Programming and erase pulse dura-
tions are minimums only. When the stop timer termi-
nates a program or erase operation, the device en-
ters an inactive state and remains inactive until re-
ceiving the appropriate verify or reset command.
Write Protection
The command register is only active when V
PP
is at
high voltage. Depending upon the application, the
system designer may choose to make the V
PP
pow-
er supply switchableDavailable only when memory
updates are desired. When V
PP
e
V
PPL
, the con-
6
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PDF描述 |
|---|---|
| P28F010-150 | 1024K (128K x 8) CMOS FLASH MEMORY |
| P28F020-90 | 28F020 2048K (256K X 8) CMOS FLASH MEMORY |
| P28F020-120 | 28F020 2048K (256K X 8) CMOS FLASH MEMORY |
| P28F020-150 | 28F020 2048K (256K X 8) CMOS FLASH MEMORY |
| P28F256A-120 | x8 Flash EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P28F010150 | 制造商:INTEL 功能描述:* |
| P28F010-150 | 制造商:Intel 功能描述: |
| P28F010-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
| P28F010-65 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1024K (128K x 8) CMOS FLASH MEMORY |
| P28F010-90 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1024K (128K x 8) CMOS FLASH MEMORY |
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