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參數資料
| 型號： | P28F020-120 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 28F020 2048K (256K X 8) CMOS FLASH MEMORY |
| 中文描述： | 256K X 8 FLASH 12V PROM, 120 ns, PDIP32 |
| 封裝： | 0.620 X 1.640 INCH, PLASTIC, DIP-32 |
| 文件頁數： | 6/38頁 |
| 文件大小： | 878K |
| 代理商： | P28F020-120 |
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28F020
E
6
Erase Voltage
Switch
Input/Output
Buffers
PGM Voltage
Switch
Chip Enable
Output Enable
Logic
Data Latch
State
Control
Command
Register
Integrated Stop
Timer
Y-Decoder
X-Decoder
A
Y-Gating
2,097,152 Bit
Cell Matrix
To Array Source
V
CC
V
SS
V
PP
WE#
CE#
OE#
A
0
- A
17
STB
STB
DQ
0
- DQ
7
0245_01
Figure 1. 28F020 Block Diagram
Table 1. Pin Description
Symbol
Type
Name and Function
A
0
–A
17
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are
internally latched during a write cycle.
DQ
0
–DQ
7
INPUT/OUTPUT
DATA INPUT/OUTPUT:
Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active
high and float to tri-state
off
when the chip is deselected or the
outputs are disabled. Data is internally latched during a write cycle.
CE#
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CE# is active low; CE# high
deselects the memory device and reduces power consumption to
standby levels.
OE#
INPUT
OUTPUT ENABLE:
Gates the devices output through the data
buffers during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the control register and the
array. Write enable is active low. Addresses are latched on the
falling edge and data is latched on the rising edge of the WE#
pulse.
Note:
With V
PP
≤
6.5 V, memory contents cannot be altered.
ERASE/PROGRAM POWER SUPPLY
for writing the command
register, erasing the entire array, or programming bytes in the array.
V
PP
V
CC
V
SS
DEVICE POWER SUPPLY
(5 V ±10%)
GROUND
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