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參數(shù)資料
| 型號(hào)： | P82C55A |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CHMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 1/23頁 |
| 文件大?。?/td> | 325K |
| 代理商： | P82C55A |
October 1995
Order Number: 231256-004
82C55A
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Y
Compatible with all Intel and Most
Other Microprocessors
Y
High Speed, ‘‘Zero Wait State’’
Operation with 8 MHz 8086/88 and
80186/188
Y
24 Programmable I/O Pins
Y
Low Power CHMOS
Y
Completely TTL Compatible
Y
Control Word Read-Back Capability
Y
Direct Bit Set/Reset Capability
Y
2.5 mA DC Drive Capability on all I/O
Port Outputs
Y
Available in 40-Pin DIP and 44-Pin PLCC
Y
Available in EXPRESS
D Standard Temperature Range
D Extended Temperature Range
The Intel 82C55A is a high-performance, CHMOS version of the industry standard 8255A general purpose
programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides
24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation.
The 82C55A is pin compatible with the NMOS 8255A and 8255A-5.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In
MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used
for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration.
The 82C55A is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent NMOS product. The 82C55A is available in 40-pin
DIP and 44-pin plastic leaded chip carrier (PLCC) packages.
231256–1
Figure 1. 82C55A Block Diagram
231256–31
231256–2
Figure 2. 82C55A Pinout
Diagrams are for pin reference only. Package
sizes are not to scale.
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