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參數(shù)資料
| 型號： | P83C661X2BBD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family |
| 中文描述： | 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-389-1, LQFP-44 |
| 文件頁數(shù)： | 31/102頁 |
| 文件大?。?/td> | 584K |
| 代理商： | P83C661X2BBD |
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Philips Semiconductors
Product data
P8xC660X2/661X2
80C51 8-bit microcontroller family
16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
2
C interfaces
2003 Oct 02
31
SIO1 and SIO2, I
2
C Serial I/O
The I
2
C-bus is a simple bi-directional 2-wire bus to transfer
information between devices connected to the bus. The main
features of the bus are:
Only two bus lines are required: a serial clock line (SCL) and a
serial data line (SDA).
Bi-directional data transfer between masters and slaves.
Each device connected to the bus is software addressable by a
unique address.
Masters can operate as Master-transmitter or as Master-receiver.
It is a true multi-master bus (no central master) and includes
collision detection and arbitration to prevent data corruption if two
or more masters simultaneously initiate data transfer.
Serial clock synchronization allows devices with different bit rates
to communicate via the same serial bus.
Serial clock synchronization can be used as a handshake
mechanism to suspend and resume serial transfer.
Devices can be added to or removed from an I
2
C-bus system
without affecting any other device on the bus.
Fault diagnostics and debugging are simple; malfunctions can be
immediately traced.
For more information see the Philips publication “The I
2
C-Bus
Specification”, especially for detailed descriptions of the Fast and
the Standard data-transfer modes. Also, refer to the data sheets for
the 8xC552, the 8xC554, the 8xC557, and the 8xC65x.
The SIO1 I
2
C serial port interface has a selectable bi-directional
data-transfer mode, either the 400Kbit/s Fast-mode or the 100Kbit/s
Standard-mode. In the Fast-mode, the port performance and the
register definitions are identical to those of the 8xC557 devices, and
in the Standard-mode (the reset default), they are identical to those
of the 8xC652, 8xC654, 8xC552, and 8xC554 devices.
The Fast-mode is functionally the same as the Standard-mode
except for the bit rate selection (see Tables 7 and 8), the timing
of the SCL and SDA signals (see the I
2
C electrical
characteristics), and the output slew-rate control. The
Fast-mode allows up to a four-fold bit-rate increase over that of
the Standard-mode, and yet, it is downward compatible with the
Standard-mode, i.e. it can be used in a 0 to 100Kbit/s bus
system.
The SCL serial port for the clock line of the I
2
C bus is an alternate
function of the P1.6 port pin, and the SDA serial port for the data line
of the I
2
C bus is an alternate function of the P1.7 port pin.
Consequently, these 2 port pins are open drain outputs (no
pull-ups), and the output latches of P1.6 and P1.7 must be set to
logic 1 in order to enable the SIO1 outputs.
The second I
2
C serial port of the 8xC661X2, SIO2, has the
400Kbit/s Fast data-transfer mode only and selectable slew-rate
control of the output pins. It also has the same port performance
and register definitions as those of the 8xC557. The SCL1 and
SDA1 serial ports have dedicated pins with open-drain outputs and
Schmitt-trigger inputs.
There is an analog circuit for controlling the turn-on and turn-off
rates of the output pull-down (slew-rate control circuit) which is
required to meet the electrical specifications of the Fast-mode under
nominal conditions (5 V). To achieve the maximum slew-rates, the
circuit must be disabled. For the SIO1 serial port, the slew-rate
control circuits for both the SCL and SDA pins are disabled in the
Standard mode (maximum slew-rate), and they are enabled in the
Fast-mode. For the SIO2 serial port, the slew-rate control circuits
for both pins are enabled by reset, but the Slew-Rate Disable bit
(SRD bit) in the AUXR Register disables the slew-rate circuits for
both the SCL1 and SDA1 pins when set for maximum slew-rates.
This feature of the SIO2 slew-rate control is very useful for higher
bus loads, higher temperatures and lower voltages that cause
additional decreases in slew-rates.
All of the functional descriptions discussed below apply to
both the SIO1 and the SIO2 I
2
C serial ports although the text
may refer to the SIO1 only. See page 10 for the corresponding
SIO2 register addresses.
The I
2
C on-chip logic performs a byte oriented data transfer, clock
generation, address recognition and bus control arbitration, and
interfaces to the external I
2
C-bus via the two port pins SCL and
SDA. It meets the I
2
C-bus specification and supports all transfer
modes (other than the low-speed mode) from-and-to the I
2
C-bus.
The logic handles byte transfers autonomously. It also keeps track
of serial transfers, and a status register (SxSTA) reflects the status
of the SIOx logic and the I
2
C-bus.
The CPU interfaces to the logic of each of the two I
2
Cs via the
following four Special Function Registers (where x=1,2):
SxCON: Control register, bit addressable by the CPU.
SxSTA: Status register whose contents may be used as a vector
to service routines.
SxDAT: Data shift register; the data byte is stable as long as the
SI bit = 1 (SxCON.3).
SxADR: Slave address register; its LSB enables / disables
general call address recognition.
A typical I
2
C-bus configuration is shown in Figure 15, and Figure 16
shows how a data transfer is accomplished on the bus. Depending
on the state of the direction bit (R/W), two types of data transfers are
possible on the I
2
C-bus:
1. Data transfer from a master transmitter to a slave receiver. The
first byte transmitted by the master is the slave address. Next
follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver. The
first byte (the slave address) is transmitted by the master. The
slave then returns an acknowledge bit. Next follows the data
bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last
byte. At the end of the last received byte, a “not acknowledge” is
returned.
The master device generates all of the serial clock pulses and the
START and STOP conditions. A transfer is ended with a STOP
condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the
I
2
C bus will not be released.
Modes of Operation:
The on-chip SIO1 logic may operate in the
following four modes:
1. Master Transmitter Mode:
Serial data output through P1.7/SDA while P1.6/SCL outputs the
serial clock. The first byte transmitted contains the slave address
相關(guān)PDF資料 |
PDF描述 |
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| P83C661X2FA | 80C51 8-bit microcontroller family |
| P83C661X2 | 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces |
| P83C660X2 | 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces |
| P87C660X2 | 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces |
| P87C661X2 | 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P83C661X2FA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family |
| P83C748EBAA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count |
| P83C748EBDDB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count |
| P83C748EBPN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count |
| P83C748EFA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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