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參數(shù)資料
| 型號： | P83C661X2BBD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family |
| 中文描述： | 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-389-1, LQFP-44 |
| 文件頁數(shù)： | 87/102頁 |
| 文件大?。?/td> | 584K |
| 代理商： | P83C661X2BBD |
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Philips Semiconductors
Product data
P8xC660X2/661X2
80C51 8-bit microcontroller family
16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
2
C interfaces
2003 Oct 02
87
I
2
C-BUS INTERFACE TIMING (5 V, 3.5 MHZ TO 16 MHZ) NOT TESTED, GUARANTEED BY DESIGN
All values referred to V
IH(min)
and V
IL(max)
levels; see Figure TBD
Symbol
Figure
Parameter
I
2
C-BUS
STANDARD MODE
MIN
Unit
FAST MODE
MIN
MAX
MAX
f
SCL
t
BUF
SCL clock frequency
Bus free time between a STOP and START
condition
Hold time (repeated) START condition. After this
period, the first clock pulse is generated
LOW period of the SCL clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time:
– for CBUS compatible masters (notes 1, 3)
– for I
2
C–bus devices (notes 1, 2)
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
0
4.7
100
–
0
1.3
400
–
kHz
μ
s
t
HD; STA
4.0
–
0.6
–
μ
s
t
LOW
t
HIGH
t
SU; STA
t
HD;DAT
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
μ
s
μ
s
μ
s
μ
s
5.0
0
–
–
–
0
–
0.9
t
SU;DAT
t
FD
, t
FC
t
FD
, t
FC
t
SU; STO
C
b
t
SP
250
–
–
4.0
–
–
–
1000
300
–
400
–
100
3
20 + 0.1 c
b4
–
300
ns
ns
0.6
–
0
–
400
50
μ
s
pF
ns
NOTES:
1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
2. The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW)
of the SCL signal.
3. A fast mode I
2
C-bus device can be used in a standard mode I
2
C-bus system, but the requirement t
SU, DAT
> 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t
R(max)
+ t
SU<DAT
= 1000 + 250 = 1250 ns (according to the standard-mode
I
2
C-bus specification) before the SCL line is released.
4. C
b
= total capacitance of one bus line in pF.
相關(guān)PDF資料 |
PDF描述 |
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| P83C661X2FA | 80C51 8-bit microcontroller family |
| P83C661X2 | 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces |
| P83C660X2 | 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces |
| P87C660X2 | 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces |
| P87C661X2 | 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P83C661X2FA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family |
| P83C748EBAA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count |
| P83C748EBDDB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count |
| P83C748EBPN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count |
| P83C748EFA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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