參數(shù)資料
型號(hào)： P83C661X2BBD
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family
中文描述： 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-389-1, LQFP-44
文件頁(yè)數(shù)： 69/102頁(yè)
文件大?。?/td> 584K
代理商： P83C661X2BBD
Philips Semiconductors
Product data
P8xC660X2/661X2
80C51 8-bit microcontroller family
16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
2
C interfaces
2003 Oct 02
69
CMOD
Address = D9H
Reset Value = 00XX X000B
CIDL
WDTE
–
–
–
CPS1
CPS0
ECF
Bit:
Symbol
Function
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
Not implemented, reserved for future use.*
PCA Count Pulse Select bit 1.
PCA Count Pulse Select bit 0.
CPS1
CPS0
Selected PCA Input**
0
0
0
Internal clock, f
OSC
/6 in 6-clock mode (f
OSC
/12 in 12-clock mode)
0
1
1
Internal clock, f
OSC
/2 in 6-clock mode (f
OSC
/4 in 12-clock mode)
1
0
2
Timer 0 overflow
1
1
3
External clock at ECI/P1.2 pin
(max. rate = f
OSC
/4 in 6-clock mode, f
OCS
/8 in 12-clock mode)
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
WDTE
–
CPS1
CPS0
ECF
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** f
OSC
= oscillator frequency
SU01318
7
6
5
4
3
2
1
0
Figure 38. CMOD: PCA Counter Mode Register
CCON
Address = D8H
Reset Value = 00X0 0000B
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
Bit Addressable
Bit:
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
Not implemented, reserved for future use*.
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01319
7
6
5
4
3
2
1
0
Figure 39. CCON: PCA Counter Control Register
相關(guān)PDF資料
PDF描述
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參數(shù)描述
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