參數(shù)資料
型號: P83C661X2BBD
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 80C51 8-bit microcontroller family
中文描述: 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-389-1, LQFP-44
文件頁數(shù): 64/102頁
文件大?。?/td> 584K
代理商: P83C661X2BBD
Philips Semiconductors
Product data
P8xC660X2/661X2
80C51 8-bit microcontroller family
16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
2
C interfaces
2003 Oct 02
64
Interrupt Priority Structure
The P8xC660X2/661X2 has an 8/9 source four-level interrupt
structure (see Table 15).
There are 4 SFRs associated with the four-level interrupt. They are
the IE, IEN1, IP, and IPH. (See Figures 31, 32, and 33.) The IPH
(Interrupt Priority High) register makes the four-level interrupt
structure possible. The IPH is located at SFR address B7H.
The function of the IPH SFR, when combined with the IP SFR,
determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Table 14.
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
Table 15.
Interrupt Table P8xC661X2
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
N (L)
1
VECTOR ADDRESS
X0
1
IE0
Y (T)
2
03H
SIO1 (I2C)
2
N
2BH
SIO2 (I2C)
3
N
43H
T0
4
TP0
Y
0BH
X1
5
IE1
N (L)
Y (T)
13H
T1
6
TF1
Y
1BH
SP
7
RI, TI
N
23H
T2
8
TF2, EXF2
N
3BH
PCA
9
CF, CCFn
n = 0–4
N
33H
NOTES:
1. L = Level activated
2. T = Transition activated
Table 16.
Interrupt Table P8xC662X2
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
N (L)
1
VECTOR ADDRESS
X0
1
IE0
Y (T)
2
03H
SIO1 (I2C)
2
N
2BH
T0
3
TP0
Y
0BH
X1
4
IE1
N (L)
Y (T)
13H
T1
5
TF1
Y
1BH
SP
6
RI, TI
N
23H
T2
7
TF2, EXF2
N
3BH
PCA
8
CF, CCFn
n = 0–4
N
33H
NOTES:
1. L = Level activated
2. T = Transition activated
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
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